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    Method for manufacturing a TFT SRAM memory device with improved performance
    31.
    发明授权
    Method for manufacturing a TFT SRAM memory device with improved performance 失效
    制造具有改进性能的TFT SRAM存储器件的方法

    公开(公告)号：US5953606A

    公开(公告)日：1999-09-14

    申请号：US67151

    申请日：1998-02-27

    Applicant: Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

    Inventor： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

    IPC: H01L21/8244 ,  H01L27/11

    CPC classification number: H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    Abstract: A method of forming a contact between a conductor and a substrate region in a MOSFET SRAM starts with forming a dielectric layer on the surface of a partially completed SRAM device with pass and latch transistors covering the transistors. Then, form a thin film gate electrode and an interconnect on the dielectric layer with a gate oxide layer covering the gate electrode and the interconnect; cover the gate oxide layer with a poly conductive layer. Then form a silicon oxide layer over the poly conductive layer and pattern the silicon oxide layer to form a silicon oxide channel mask over the poly conductive layer which is used to pattern the silicon oxide layer into a channel mask over the gate electrode. The channel mask is used for patterning the implanting of dopant into the poly conductive layer aside from the channel mask to form a source region, a drain region and an interconnect in the poly conductive layer. Then form a contact through the gate oxide layer between the interconnect and the poly conductive layer by forming a tungsten layer over the poly conductive layer aside from the channel mask which remains in place.

    Abstract translation: 在MOSFET SRAM中形成导体和衬底区域之间的接触的方法开始于在部分完成的SRAM器件的表面上形成覆盖晶体管的通过和锁存晶体管的介质层。 然后，在电介质层上形成薄膜栅电极和互连，其中覆盖栅极和互连的栅氧化层; 用多导电层覆盖栅极氧化层。 然后在多导电层上形成氧化硅层，并对氧化硅层进行图案化以在多晶硅导电层上形成氧化硅沟道掩模，该导电层用于将氧化硅层图案化成栅电极上的沟道掩模。 沟道掩模用于图案化掺杂剂注入到沟道掩模之外的多导电层中以在多导电层中形成源极区域，漏极区域和互连。 然后通过在保持在适当位置的通道掩模之外的多导电层上形成钨层，通过互连和多导电层之间的栅极氧化层形成接触。

    Method of forming an embedded memory device
    33.
    发明授权
    Method of forming an embedded memory device 有权
    形成嵌入式存储器件的方法

    公开(公告)号：US09082705B2

    公开(公告)日：2015-07-14

    申请号：US13566710

    申请日：2012-08-03

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

    CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/42356 ,  H01L29/66833 ,  H01L29/792

    Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

    Abstract translation: 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

    Semiconductor devices and methods for fabricating the same
    35.
    发明授权
    Semiconductor devices and methods for fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08012836B2

    公开(公告)日：2011-09-06

    申请号：US11528405

    申请日：2006-09-28

    Applicant: Kuo-Chyuan Tzeng ,  Jian-Yu Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chin-Yang Chang

    Inventor： Kuo-Chyuan Tzeng ,  Jian-Yu Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chin-Yang Chang

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10894

    Abstract: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件的示例性实施例包括在其中形成有多个隔离结构的衬底，其在衬底上限定第一和第二区域。 晶体管分别形成在第一和第二区域中的衬底的一部分上，其中第二区域中的晶体管仅在与衬底的漏极区相邻的衬底中仅形成一个凹坑掺杂区域。 第一电介质层形成在衬底上，覆盖形成在第一和第二区域中的晶体管。 通过第一介电层形成多个第一接触插塞，分别在第二区域中电连接晶体管的源极区域和漏极区域。 在第一电介质层上形成第二电介质层，其中形成有电容器，其中电容器电连接第一接触插塞之一。

    DATA STORAGE DEVICE CARRIER SYSTEM
    36.
    发明申请
    DATA STORAGE DEVICE CARRIER SYSTEM 有权
    数据存储设备载体系统

    公开(公告)号：US20100281199A1

    公开(公告)日：2010-11-04

    申请号：US12433544

    申请日：2009-04-30

    Applicant: Chi-Chang Fu ,  Kuo Ching Huang ,  Feng-Cheng Su ,  Jason Alan Yelinek

    Inventor： Chi-Chang Fu ,  Kuo Ching Huang ,  Feng-Cheng Su ,  Jason Alan Yelinek

    IPC: G06F13/00

    CPC classification number: G06F13/4068 ,  G06F13/12 ,  G06F13/409 ,  G06F13/4282

    Abstract: A data storage device carrier system includes a carrier configured to support one or more data storage devices, a backplane, including one or more coupling connector devices configured to electrically couple with a motherboard, and an interposer board operable to couple a plurality of the data storage devices supported by the carrier with the backplane. In an embodiment, the one or more coupling connector devices are operable to transfer communication signals and electrical power. The interposer board is operable to provide the electrical power from a single port on the backplane to each of the plurality of the data storage devices. The interposer board is also operable to pass communication signals between a primary port on the backplane to a first one of the plurality of the data storage devices, and to pass communication signals between a secondary port on the backplane to a second one of the plurality of the data storage devices.

    Abstract translation: 数据存储设备载体系统包括被配置为支持一个或多个数据存储设备的载体，包括被配置为与母板电耦合的一个或多个耦合连接器设备的背板以及可操作以将多个数据存储器 载体与背板支持的设备。 在一个实施例中，一个或多个耦合连接器装置可操作以传送通信信号和电力。 插入器板可操作以将电力从背板上的单个端口提供给多个数据存储设备中的每一个。 插入器板还可操作地将背板上的主端口之间的通信信号传送到多个数据存储设备中的第一个，并将背板上的辅助端口之间的通信信号传递到多个 数据存储设备。

    Securing device
    39.
    发明授权
    Securing device 失效
    固定装置

    公开(公告)号：US06909085B2

    公开(公告)日：2005-06-21

    申请号：US10456885

    申请日：2003-06-06

    Applicant: Kuo-Ching Huang

    Inventor： Kuo-Ching Huang

    IPC: H04N1/028 ,  H04N1/03 ,  H04N1/19 ,  H01J40/14 ,  H01J5/02

    CPC classification number: H04N1/03 ,  H04N2201/02456 ,  H04N2201/02474 ,  H04N2201/02485

    Abstract: A securing device includes a sustaining member, a plurality of threaded holes, and a plurality of screws. The sustaining member includes a clamped portion and a securing portion extending from the clamped portion. The clamped portion is interfaced between the photoelectric conversion device and the carriage module housing. The thickness of the clamped portion is even enough to keep the distance between the photoelectric conversion device and the carriage module housing constant, thereby assuring that the photoelectric conversion device is orthogonal to the central line of a lens in the carriage module housing. The securing portion is flexible so as to facilitate the assembling operation of the circuit board, the photoelectric conversion device and the carriage module housing by way of the threaded holes and screws.

    Abstract translation: 固定装置包括支撑构件，多个螺纹孔和多个螺钉。 保持构件包括夹紧部分和从夹紧部分延伸的固定部分。 夹持部分接合在光电转换装置和支架模块壳体之间。 夹持部分的厚度足以使光电转换装置和滑架模块壳体之间的距离恒定，从而确保光电转换装置与托架模块壳体中的透镜的中心线正交。 固定部分是柔性的，以便于通过螺纹孔和螺钉使电路板，光电转换装置和滑架模块壳体的组装操作。

    Integrated high performance MOS tunneling LED in ULSI technology
    40.
    发明授权
    Integrated high performance MOS tunneling LED in ULSI technology 失效
    集成高性能MOS隧道LED在ULSI技术

    公开(公告)号：US06806521B2

    公开(公告)日：2004-10-19

    申请号：US10338138

    申请日：2003-01-08

    Applicant: Dun-Nian Yaung ,  Kuo-Ching Huang

    Inventor： Dun-Nian Yaung ,  Kuo-Ching Huang

    IPC: H01L31062

    CPC classification number: H01L27/15 ,  H01L33/0004

    Abstract: A new method and structure for the combined creation of CMOS devices and LED devices. The process starts with a substrate over the surface of which are designated a first surface region for the creation of CMOS devices there-over and a second surface region for the creation of LED devices there-over. A relatively thick layer of gate oxide is created over the surface of the substrate. The first surface region is blocked by a mask of photoresist after which the second surface region is exposed to a plasma etch, thereby providing roughness to the surface of the relatively thick layer of gate oxide and reducing the thickness thereof. The blocking mask is removed, additional oxidation of the exposed surface creates a relatively thick layer of gate oxide over the first surface area and a relatively thin layer of gate oxide over the second surface area.

    Abstract translation: 一种用于组合创建CMOS器件和LED器件的新方法和结构。 该过程从其表面上的衬底指定为用于在其上形成CMOS器件的第一表面区域和用于在其上形成LED器件的第二表面区域开始。 在衬底的表面上形成较厚的栅极氧化层。 第一表面区域被光致抗蚀剂掩模阻挡，之后第二表面区域暴露于等离子体蚀刻，从而为栅极氧化物的较厚层的表面提供粗糙度并减小其厚度。 去除阻挡掩模，暴露表面的额外氧化在第一表面区域上形成相对厚的栅极氧化物层，并在第二表面区域上形成相当薄的栅极氧化物层。

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