公开(公告)号：US11030131B2

公开(公告)日：2021-06-08

申请号：US16942728

申请日：2020-07-29

申请人： MICROSOFT TECHNOLOGY LICENSING, LLC

发明人： Chad Balling McBride ,  George Petre ,  Amol Ashok Ambardekar ,  Kent D. Cedola ,  Larry Marvin Wall ,  Boris Bobrov

IPC分类号： G06F7/76 ,  G06F13/16 ,  G06N3/04 ,  G06N3/063 ,  G06F12/0862 ,  G06F9/46 ,  G06F1/324 ,  G06F3/06 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/80 ,  G06F17/15 ,  G06N3/06 ,  G06N3/08 ,  G06N3/10 ,  H03M7/30 ,  H04L12/715 ,  H04L29/08 ,  G06F1/3234 ,  G06F12/02 ,  G06F13/28 ,  H03M7/46 ,  H04L12/723

摘要： The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as management of data among the various memory components of the NN/DNN. Using virtualized hardware iterators, data for processing by the NN/DNN can be traversed and configured to optimize the number of operations as well as memory utilization to enhance the overall performance of a NN/DNN. Operatively, an iterator controller can generate instructions for execution by the NN/DNN representative of one more desired iterator operation types and to perform one or more iterator operations. Data can be iterated according to a selected iterator operation and communicated to one or more neuron processors of the NN/DD for processing and output to a destination memory. The iterator operations can be applied to various volumes of data (e.g., blobs) in parallel or multiple slices of the same volume.

公开(公告)号：US11010315B2

公开(公告)日：2021-05-18

申请号：US15881519

申请日：2018-01-26

申请人： MICROSOFT TECHNOLOGY LICENSING, LLC

发明人： Amol Ashok Ambardekar ,  Aleksandar Tomic ,  Chad Balling McBride ,  George Petre ,  Kent D. Cedola ,  Larry Marvin Wall ,  Boris Bobrov

IPC分类号： G06F13/16 ,  G06N3/04 ,  G06N3/063 ,  G06F12/0862 ,  G06F9/46 ,  G06F1/324 ,  G06F3/06 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/80 ,  G06F17/15 ,  G06N3/06 ,  G06N3/08 ,  G06N3/10 ,  H03M7/30 ,  H04L12/715 ,  H04L29/08 ,  G06F1/3234 ,  G06F12/02 ,  G06F13/28 ,  H03M7/46 ,  H04L12/723

摘要： The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as memory data management of a NN/DNN. Using vector quantization of neuron weight values, the processing of data by neurons can be optimize the number of operations as well as memory utilization to enhance the overall performance of a NN/DNN. Operatively, one or more contiguous segments of weight values can be converted into one or more vectors of arbitrary length and each of the one or more vectors can be assigned an index. The generated indexes can be stored in an exemplary vector quantization lookup table and retrieved by exemplary fast weight lookup hardware at run time on the flyas part of an exemplary data processing function of the NN as part of an inline de-quantization operation to obtain needed one or more neuron weight values.

公开(公告)号：US10985775B2

公开(公告)日：2021-04-20

申请号：US14965708

申请日：2015-12-10

申请人： KYNDI, INC.

发明人： Arun Majumdar

IPC分类号： H03M7/30 ,  G06F16/2452 ,  H03M7/04 ,  H03M7/14 ,  H03M7/46 ,  G06F16/28

摘要： A method and apparatus is provided for implementing combinatorial hypermaps (CHYMAPS) and/or generalized combinatorial maps (G-Maps) based data representations and operations, comprising: mapping term-algebras to tree-based numbers using a fast algorithm and representing a graph of the mapping structure as a CHYMAPS using reversible numeric encoding and decoding; generating a representation of CHYMAPS in a form optimized for sub-map (sub-graph) to map (graph) isomorphism and partial matching with a general matching process; performing operations on the CHYMAPS as operations on respective numerical representations; performing compression and decompression using a three bit self-delimiting binary code; and storing and retrieving codes.

公开(公告)号：US10970228B2

公开(公告)日：2021-04-06

申请号：US16220608

申请日：2018-12-14

申请人： Micron Technology, Inc.

发明人： Stephen Hanna ,  Nadav Grosz

IPC分类号： G06F3/00 ,  G06F12/1009 ,  H03M7/46 ,  G06F3/06 ,  G06F5/06

摘要： Apparatus and methods are disclosed, including using a memory controller to generate an encoded physical address using a run length encoding (RLE) algorithm on a physical address to reduce a length of the encoded physical address, and storing the encoded physical address as a map entry of a logical-to-physical (L2P)) table in a cache random access memory of the memory controller.

公开(公告)号：US10795836B2

公开(公告)日：2020-10-06

申请号：US15694663

申请日：2017-09-01

申请人： Microsoft Technology Licensing, LLC

发明人： Chad Balling McBride ,  George Petre ,  Amol Ashok Ambardekar ,  Kent D. Cedola ,  Larry Marvin Wall ,  Boris Bobrov

IPC分类号： G06F15/76 ,  G06F13/16 ,  G06N3/04 ,  G06N3/063 ,  G06F12/0862 ,  G06F9/46 ,  G06F1/324 ,  G06F3/06 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/80 ,  G06F17/15 ,  G06N3/06 ,  G06N3/08 ,  G06N3/10 ,  H03M7/30 ,  H04L12/715 ,  H04L29/08 ,  G06F1/3234 ,  G06F12/02 ,  G06F13/28 ,  H03M7/46 ,  H04L12/723

摘要： The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as management of data among the various memory components of the NN/DNN. Using virtualized hardware iterators, data for processing by the NN/DNN can be traversed and configured to optimize the number of operations as well as memory utilization to enhance the overall performance of a NN/DNN. Operatively, an iterator controller can generate instructions for execution by the NN/DNN representative of one more desired iterator operation types and to perform one or more iterator operations. Data can be iterated according to a selected iterator operation and communicated to one or more neuron processors of the NN/DD for processing and output to a destination memory. The iterator operations can be applied to various volumes of data (e.g., blobs) in parallel or multiple slices of the same volume.

公开(公告)号：US20200274552A1

公开(公告)日：2020-08-27

申请号：US16288026

申请日：2019-02-27

申请人： Movidius LTD

发明人： Valentina Rigo ,  David Bernard ,  Peter McGlynn

IPC分类号： H03M7/30 ,  H03M7/40 ,  H03M7/46

摘要： Methods, apparatus, systems and articles of manufacture to compress data are disclosed. An example apparatus includes an off-chip memory to store data; a data slicer to split a dataset into a plurality of blocks of data; a data processor to select a first compression technique for a first block of the plurality of blocks of data based on first characteristics of the first block; and select a second compression technique for a second block of the plurality of blocks of data based on second characteristics of the second block; a first compressor to compress the first block using the first compression technique to generate a first compressed block of data; a second compressor to compress the second block using the second compression technique to generate a second compressed block of data; a header generator to generate a first header identifying the first compression technique and a second header identifying the second compression technique; and an interface to transmit the first compressed block of data with the first header and the second compressed block of data with the second header to be stored in the off chip memory.

公开(公告)号：US20200186164A1

公开(公告)日：2020-06-11

申请号：US16779851

申请日：2020-02-03

申请人： GE VIDEO COMPRESSION, LLC

发明人： Detlev MARPE ,  Tung NGUYEN ,  Heiko SCHWARZ ,  Thomas WIEGAND

IPC分类号： H03M7/00 ,  H03M7/40 ,  H03M7/46

摘要： Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n−1, the value of si corresponds to a range of the ith partition.

公开(公告)号：US10574261B2

公开(公告)日：2020-02-25

申请号：US15997183

申请日：2018-06-04

申请人： Maxlinear, Inc.

发明人： Curtis Ling ,  Jining Duan

IPC分类号： H03M7/30 ,  H03M7/46 ,  H03M7/40 ,  H03M1/00 ,  H03M1/66

摘要： A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal.

公开(公告)号：US20190229749A1

公开(公告)日：2019-07-25

申请号：US16124085

申请日：2018-09-06

申请人： NVIDIA Corp.

发明人： Sunil Sudhakaran ,  Russ Newcomb ,  Rohit Rathi

IPC分类号： H03M5/14 ,  H03M5/08 ,  H03M7/46

摘要： A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.

公开(公告)号：US10178388B2

公开(公告)日：2019-01-08

申请号：US14905000

申请日：2014-07-17

申请人： Gurulogic Microsystems OY

发明人： Tuomas Karkkainen ,  Ossi Kalevo

IPC分类号： H04N19/132 ,  H03M7/40 ,  H03M7/46

摘要： A method of encoding data in an encoder to generate corresponding encoded data includes receiving the data to be encoded and analyzing sub-portions of the data to be encoded to determine one or more encoding algorithms which are to be applied to encode the sub-portions, wherein the one or more encoding algorithms include at least one interpolation algorithm; computing one or more interpolation parameters for the at least one interpolation algorithm which are representative of data values of the sub-portion of the data to be encoded by the at least one interpolation algorithm; encoding a remainder of the sub-portions of the data to be encoded using the one or more encoding algorithms; and combining data generated in the computing and encoding to generate the encoded data. A method is also disclosed for decoding encoded data in a decoder. The methods may be employed in an encoder, decoder, and codec.