公开(公告)号：US11336757B2

公开(公告)日：2022-05-17

申请号：US16820440

申请日：2020-03-16

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Thomas Anton Leyrer ,  Peter Aberl

IPC分类号： H04L29/08 ,  H04L69/323 ,  G06F5/06

摘要： A circuit includes a buffer, a first programmable real-time unit (PRU), and a second PRU. The first PRU is coupled to the buffer and configured to couple to an input interface. The first PRU is further configured to receive first data sampled by the input interface and receive second data sampled by the input interface. The first PRU is further configured to multiplex the first data and the second data to generate multiplexed data and transmit the multiplexed data to the buffer. The second PRU is coupled to the buffer and configured to couple to an output interface. The second PRU is further configured to obtain the multiplexed data from the buffer and transmit the multiplexed data via an Ethernet physical layer.

公开(公告)号：US11294721B2

公开(公告)日：2022-04-05

申请号：US16940214

申请日：2020-07-27

申请人： Marvell Asia Pte, Ltd.

发明人： Nathan Chrisman

IPC分类号： G06F9/50 ,  G06F12/0893 ,  G06F9/448 ,  G06F12/02 ,  G06F9/54 ,  G06F9/38 ,  G06F11/10 ,  G06F5/06 ,  G06F13/16

摘要： Systems and corresponding methods employ an object-oriented (OO) memory (OOM) to effect inter-hardware-client (IHC) communication among a plurality of hardware clients included in same. A system comprises a centralized OOM and the plurality of hardware clients communicate, directly, to the centralized OOM device via OO message transactions. The centralized OOM device effects IHC communication among the plurality of hardware clients based on the OO message transactions. Another system comprises a plurality of OO memories (OOMs) capable of inter-object-oriented-memory-device communication. A hardware client communicates, directly, to a respective OOM device via OO message transactions. The inter-object-oriented-memory-device communication effects IHC communication among the plurality of hardware clients based on the OO message transactions.

公开(公告)号：US11255749B2

公开(公告)日：2022-02-22

申请号：US16464107

申请日：2017-11-24

申请人： AVL LIST GMBH

发明人： Helmut Kokal

IPC分类号： G01M13/026 ,  G01L3/22 ,  G06F5/06 ,  H03H21/00

摘要： The invention relates to a device and to a method for controlling a test stand arrangement having a specimen and having a loading machine, which is connected to the specimen by a connecting shaft. An estimated value (TE,est) for for the internal torque (TE) of the specimen is determined and, from the estimated value (TE,est), while taking into account a natural frequency (f0) and a delay, a damping signal (TDamp) is determined and fed back into the control loop.

公开(公告)号：US11238334B2

公开(公告)日：2022-02-01

申请号：US16569307

申请日：2019-09-12

申请人： Hailo Technologies Ltd.

发明人： Avi Baum ,  Or Danon ,  Daniel Ciubotariu

IPC分类号： G06N3/063 ,  G06F5/06 ,  G06F5/10 ,  G06F7/78 ,  G06F9/30 ,  G06N3/04 ,  G06N3/08

摘要： A novel and useful system and method of input alignment for streamlining vector operations that reduce the required memory read bandwidth. The input aligner as deployed in the NN processor, functions to facilitate the reuse of data read from memory and to avoid having to re-read that data in the context of neural network calculations. The input aligner functions to distribute input data (or weights) to the appropriate compute elements while consuming input data in a single cycle. Thus, the input aligner is operative to lower the required read bandwidth of layer input in an ANN. This reflects the fact that normally in practice, a vector multiplication is performed every time instance. This considers the fact that in many native calculations that take place in an ANN, the same data point is involved in multiple calculations.

公开(公告)号：US11232347B2

公开(公告)日：2022-01-25

申请号：US16603184

申请日：2018-04-17

申请人： Cerebras Systems Inc.

发明人： Sean Lie ,  Michael Morrison ,  Michael Edwin James ,  Srikanth Arekapudi ,  Gary R. Lauterbach

IPC分类号： G06F9/30 ,  G06N3/04 ,  G06F5/06 ,  G06N3/063 ,  G06F13/00 ,  G06N3/08 ,  H04L12/935 ,  G06F9/38 ,  H04L12/54 ,  G06F13/40 ,  H04L12/931 ,  G06F30/392

摘要： Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Instructions executed by the compute element include operand specifiers, some specifying a data structure register storing a data structure descriptor describing an operand as a fabric vector or a memory vector. The data structure descriptor further describes various attributes of the fabric vector: length, microthreading eligibility, number of data elements to receive, transmit, and/or process in parallel, virtual channel and task identification information, whether to terminate upon receiving a control wavelet, and whether to mark an outgoing wavelet a control wavelet.

公开(公告)号：US11209878B2

公开(公告)日：2021-12-28

申请号：US16441637

申请日：2019-06-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jui-Cheng Huang ,  Yi-Hsing Hsiao ,  Yu-Jie Huang ,  Tsung-Tsun Chen ,  Allen Timothy Chang

IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G06F1/20

摘要： In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.

公开(公告)号：US11169951B2

公开(公告)日：2021-11-09

申请号：US17096896

申请日：2020-11-12

申请人： Altera Corporation

发明人： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC分类号： G06F13/42 ,  H04L29/06 ,  G06F5/06 ,  H04L12/947

摘要： Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US20210303980A1

公开(公告)日：2021-09-30

申请号：US17108927

申请日：2020-12-01

申请人： POSTECH Research and Business Development Foundation

发明人： Sungju RYU ,  Jae-Joon KIM ,  Youngtaek OH

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06F5/06

摘要： A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.

公开(公告)号：US20210240482A1

公开(公告)日：2021-08-05

申请号：US15734729

申请日：2019-06-06

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Stéphane CHEVOBBE ,  Marc DURANTON

IPC分类号： G06F9/38 ,  G06F5/06 ,  G06F9/30 ,  G06F15/80 ,  G06F9/32

摘要： A processor having a SIMD architecture, including an array of elementary processors, each elementary processor being associated with an elementary memory cell, a central controller connected to the elementary processors by an instruction bus and a status bus. The central controller transmits a sequence of instructions in a loop, each instruction including a calculation flow indicator. Each elementary processor has an instruction filter that makes it possible to reject or take into account an instruction depending on the identifier it contains. This operating mode makes it possible to emulate a MIMD processor on a SIMD architecture.

公开(公告)号：US20210224639A1

公开(公告)日：2021-07-22

申请号：US17005140

申请日：2020-08-27

申请人： Cerebras Systems Inc.

发明人： Sean LIE ,  Gary R. LAUTERBACH ,  Michael Edwin JAMES ,  Michael MORRISON ,  Srikanth AREKAPUDI

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06F13/00 ,  G06N3/08 ,  G06F9/30 ,  H04L12/935 ,  G06F9/38 ,  H04L12/54 ,  G06F5/06 ,  G06F13/40

摘要： Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow based computations on wavelets of data. Each processing element has a compute element and a routing element. Each compute element has memory. Each router enables communication via wavelets with nearest neighbors in a 2D mesh. A compute element receives a wavelet. If a control specifier of the wavelet is a first value, then instructions are read from the memory of the compute element in accordance with an index specifier of the wavelet. If the control specifier is a second value, then instructions are read from the memory of the compute element in accordance with a virtual channel specifier of the wavelet. Then the compute element initiates execution of the instructions.