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公开(公告)号：US11681842B2
公开(公告)日：2023-06-20
申请号：US17643359
申请日：2021-12-08
申请人： Synopsys, Inc.
IPC分类号： G06F30/32 , G06F111/04
CPC分类号： G06F30/32 , G06F2111/04
摘要： Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.
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22.发明授权公开(公告)号：US11353902B2
公开(公告)日：2022-06-07
申请号：US16861340
申请日：2020-04-29
摘要： A power control semiconductor device includes: a voltage control transistor connected between an input terminal and an output terminal; a control circuit that controls the voltage control transistor in accordance with a voltage of the output terminal; and an external terminal that controls an output voltage externally. The control circuit includes: a first divider which has resistor elements connected in series to the output terminal and which divides the output voltage of the output terminal; a first error amplifier that outputs a voltage corresponding to a potential difference between a predetermined reference voltage and a voltage divided by the first divider; and an output voltage change circuit that changes the divided voltage in accordance with a voltage input to the external terminal to change the output voltage in accordance with the voltage of the external terminal.
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23.发明申请公开(公告)号：US20220066884A1
公开(公告)日：2022-03-03
申请号：US17004636
申请日：2020-08-27
发明人： Ilan MARGALIT
摘要： A chip aka integrated circuit, the chip comprising configuration register/s, typically volatile, and/or at least one on-chip non-volatile memory m typically including at least one reserved memory location, which may be reserved for storing contents of at least one typically volatile configuration register r, from among the configuration registers; and/or apparatus configured for, at least once, storing values which may be indicative of content of at least one typically volatile configuration register r from among the registers, e.g. in the on-chip non-volatile memory m, e.g. at the at least one reserved memory location.
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公开(公告)号：US20210409284A1
公开(公告)日：2021-12-30
申请号：US17471857
申请日：2021-09-10
申请人： ARTERIS, INC.
发明人： Moez CHERIF , Benoit De LESCURE
IPC分类号： H04L12/24 , G06F30/392 , G06F30/394 , G06F30/32 , H04L12/26
摘要： Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.
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公开(公告)号：US11092901B2
公开(公告)日：2021-08-17
申请号：US16795095
申请日：2020-02-19
申请人： Qoniac GmbH
发明人： Stefan Buhl , Philip Groeger , Patrick Lomtscher
摘要： Critical dimension values can be obtained from wafer structures at predefined measurement sites. Coefficients of a preset model and another model with a different term are determined using critical dimension values from the measurement sites. The models approximate the critical dimension values, the process parameters and/or correction values of the process parameters as a function of at least two position coordinates. An updated model is selected from the models based on a criterion weighting the residuals between approximated critical dimension values, the number of terms of the model and/or the order or the terms of the model.
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公开(公告)号：US11087067B2
公开(公告)日：2021-08-10
申请号：US17142314
申请日：2021-01-06
申请人： quadric.io, Inc.
IPC分类号： G06F30/30 , G06F30/398 , G06F30/337 , G06F30/373 , G06F30/27 , G06F30/32 , G06F115/10 , G06F15/80
摘要： Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.
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公开(公告)号：US11012075B2
公开(公告)日：2021-05-18
申请号：US16802927
申请日：2020-02-27
发明人： Hyungdal Kwon , Seungwook Lee , Youngnam Hwang
IPC分类号： H03K19/17 , G06F30/32 , H03K19/1776 , G06F30/327
摘要： An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.
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公开(公告)号：US20200242290A1
公开(公告)日：2020-07-30
申请号：US16739822
申请日：2020-01-10
发明人： Ikko Hamamura , Takashi Imamichi
摘要： Methods and apparatuses for designing quantum circuits include obtaining Pauli strings included in a qubit Hamiltonian. At least some of the strings are grouped, based at least partially on a judgment of whether Pauli strings are observables that are jointly measurable by entangled measurement, at least at some operators. A quantum circuit is designed based on a result obtained from the grouping.
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29.发明授权公开(公告)号：US12073156B2
公开(公告)日：2024-08-27
申请号：US17695712
申请日：2022-03-15
申请人： Synopsys, Inc.
发明人： Amit Jalota , Andrew Saunders , Aruna Kanagaraj , Douglas Chang , Eshwari Rajendran , Prashant Gupta , Rajeev Murgai , Soumitra Majumder , Vasiliki Chatzi , Balkrishna Ramchandra Rashingkar
IPC分类号： G06F30/30 , G06F30/31 , G06F30/32 , G06F30/392 , G06F30/398
CPC分类号： G06F30/31 , G06F30/32 , G06F30/392 , G06F30/398
摘要： A system determines physical design information along a logic hierarchy of a circuit design. The system accesses physical design metrics associated with different parts of a physical design of a circuit. The system accesses a logic design of the circuit comprising a hierarchy of logic blocks. The system determines the physical design metrics associated with one or more logic blocks of the hierarchy of the logic design based on a relation between the physical design and the logic design. The system configures a user interface to display the hierarchy of the logic design of the circuit along with the physical design metrics associated with the one or more logic blocks of the hierarchy. The system sends the configured user interface for display.
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公开(公告)号：US20230289501A1
公开(公告)日：2023-09-14
申请号：US17653949
申请日：2022-03-08
申请人： The Boeing Company
发明人： Nam Hoang Nguyen , Richard Joel Thompson , John R. Lowell , Marna M. Kagele , Kristen Smith Williams
摘要： A method of minimizing a cost function of a quantum computation is provided. The method comprises receiving input of an initial state of a quantum problem instance comprising a Hamiltonian with an associated cost function. The Hamiltonian is converted into a number of Pauli strings, which are used to form an operator pool. The Pauli strings in the operator pool are ranked according to how much they lower a value of the cost function with respect to the initial state. Pauli strings are iteratively added from the operator pool to a parameterized quantum circuit, in a manner to minimize circuit depth, until a variational quantum eigensolver (VQE) algorithm converges to an approximate ground state wave function generated by the parameterized quantum circuit.
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