专利检索 ap:("Synopsys, Inc.") AND inv:"Paul Eugene Richard Lippens" 第 1 页

1.

发明授权
Latency offset in pre-clock tree synthesis modeling 有权

公开(公告)号：US11681842B2

公开(公告)日：2023-06-20

申请号：US17643359

申请日：2021-12-08

申请人： Synopsys, Inc.

发明人： Kailash Pawar , Paul Eugene Richard Lippens , Darren Charles Cronquist

IPC分类号： G06F30/32 , G06F111/04

CPC分类号： G06F30/32 , G06F2111/04

摘要： Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.