公开(公告)号：US3947840A

公开(公告)日：1976-03-30

申请号：US497992

申请日：1974-08-16

申请人： Magnus George Craford ,  Paul T. Bailey

发明人： Magnus George Craford ,  Paul T. Bailey

IPC分类号： G09F9/33 ,  G09G3/32 ,  H01L27/00 ,  H01L33/00 ,  G08B5/36

CPC分类号： H01L27/00 ,  G09G3/32 ,  H01L24/14 ,  H01L33/00 ,  H01L2224/16225 ,  H01L2924/14 ,  Y10S148/038 ,  Y10S148/065 ,  Y10S148/072 ,  Y10S148/099 ,  Y10S148/119

摘要： An integrated LED display array wherein light is emitted and observed through a light-transmissive substrate, i.e., single crystal, which carries a plurality of optically isolated LED assemblies. Scattering of light from individual assemblies is prevented by an optically absorbing doped region which optically isolates each assembly. Light is generated at the back of the single crystal and viewed through the crystal. The LED assemblies, preferably multicolor, are directly mated to energizing electronic circuitry, e.g., a monolithic integrated circuit, via appropriate interconnections sandwiched between the two. The energizing electronic circuitry comprise an array of circuit elements which provide the energizing currents for respective ones of the LED assemblies.

摘要翻译： 一种集成的LED显示阵列，其中通过承载多个光学隔离的LED组件的透光基板即单晶体发射和观察光。 通过光学吸收掺杂区域防止来自各个组件的光的散射，其光学地隔离每个组件。 光在单晶的背面产生并通过晶体观察。 LED组件，优选多色，通过夹在两者之间的适当互连，直接配合到激励电子电路，例如单片集成电路。 激励电子电路包括为各LED组件提供激励电流的电路元件阵列。

公开(公告)号：US3916430A

公开(公告)日：1975-10-28

申请号：US34105873

申请日：1973-03-14

申请人： RCA CORP

发明人： HEUNER ROBERT CHARLES ,  MORGAN DAVID KEITH ,  STEUDEL GOETZ WOLFGANG

IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H03K5/02 ,  H03K19/0185 ,  H03K1/00 ,  H03K3/26 ,  H03K3/353

CPC分类号： H01L27/0927 ,  H01L27/0218 ,  H03K5/023 ,  H03K19/018521 ,  Y10S148/038

摘要： An integrated circuit, formed on a common substrate, having one portion operated from a first source of operating potential and another portion operated from a second source of operating potential. Separate wells are diffused in said substrate for the connection thereto of the different voltages and a reference potential common to the two sources of operating potential is applied to the common substrate. Transistors having a given potential applied to their source electrodes are formed in the common substrate or in a well having the same given potential connected thereto for eliminating potential differences between the source and the substrate of the transistors.

摘要翻译： 形成在公共基板上的集成电路，其具有从第一操作电位操作的一部分和从第二操作电位操作的另一部分。 单独的阱扩散在所述衬底中用于连接到不同电压，并且将两个工作电位源公共的参考电位施加到公共衬底。 具有施加到其源电极的给定电位的晶体管形成在公共衬底或具有与其连接的相同给定电位的阱中，以消除晶体管的源极和衬底之间的电位差。

公开(公告)号：US3735210A

公开(公告)日：1973-05-22

申请号：US3735210D

申请日：1971-06-07

申请人： RCA CORP

发明人： KALISH I ,  KHAJEZADEH H

IPC分类号： H01L27/00 ,  H01L29/866 ,  H01L9/00

CPC分类号： H01L29/866 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/145

摘要： An improved zener diode for monolithic integrated circuits includes a first diffused region of one type conductivity having two portions, one of which portions has a significantly higher maximum impurity concentration than the other portion. A second diffused region of opposite type high conductivity is disposed within both portions of the first region and is separated from each by a PN junction, the PN junction between the second region and the lower conductivity portion being at a significantly greater depth than the PN junction between the second region and the high impurity concentration portion. The electrical contact to the second region is made only over the lower impurity concentration portion where the PN junction is at a significantly greater depth.

摘要翻译： 用于单片集成电路的改进的齐纳二极管包括具有两个部分的一种导电型的第一扩散区域，其中一个部分具有比其他部分显着更高的最大杂质浓度。 相反类型的高导电性的第二扩散区域设置在第一区域的两个部分内，并且由每个PN结分开，第二区域和下部导电部分之间的PN结比PN结明显更大的深度 在第二区域和高杂质浓度部分之间。 与第二区域的电接触只在PN结处于较大深度的较低杂质浓度部分上进行。

公开(公告)号：US5541137A

公开(公告)日：1996-07-30

申请号：US330170

申请日：1994-10-27

申请人： Monte Manning ,  Shubneesh Batra ,  Charles H. Dennison

发明人： Monte Manning ,  Shubneesh Batra ,  Charles H. Dennison

IPC分类号： H01L21/285 ,  H01L21/225 ,  H01L21/28

CPC分类号： H01L21/28525 ,  Y10S148/038 ,  Y10S148/123

摘要： The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

摘要翻译： 本发明的方法引入了一种在半导体器件中的支撑衬底上形成导电掺杂触点的方法，其使导电掺杂剂的侧向向外扩散最小化，并且还通过以下步骤提供低电阻接触：制备导电区域 接受接触形成; 在所述导电区域上形成磷原位掺杂多晶硅层; 在磷原位掺杂多晶硅层上形成砷原位掺杂的多晶硅层，其中两个本征掺杂的多晶硅层在不同的沉积步骤中依次沉积; 并在约900℃-1100℃的温度范围内对层进行退火，从而进行足够的热处理以使磷原子分解形成在导电区域和磷原位掺杂多晶硅层之间的第一界面二氧化硅层。

公开(公告)号：US4963509A

公开(公告)日：1990-10-16

申请号：US450223

申请日：1989-12-12

申请人： Yutaka Yoshizawa ,  Akira Uemura

发明人： Yutaka Yoshizawa ,  Akira Uemura

IPC分类号： H01L21/22

CPC分类号： H01L21/221 ,  Y10S148/038 ,  Y10S148/062 ,  Y10S438/904

摘要： Gold is diffused into a silicon substrate by first depositing an ultrathin layer of gold on one of the main faces of the substrate and then by heating the substrate to a temperature range of about 300.degree.-850.degree. C., instead of to about 1000.degree. according to the prior art. Then, following the removal of the remaining gold layer from over the substrate, the latter is reheated to a higher temperature ranging from about 700.degree. C. to about 1000.degree. C. for activating the diffused gold. The gold diffusion at the reduced temperature serves to decrease the surface irregularities of the substrate as a result of gold-silicon alloy zones created at the interface between gold layer and silicon substrate during the thermal diffusion process.

摘要翻译： 通过首先在衬底的一个主面上沉积超薄金层，然后通过将衬底加热到​​约300-850℃的温度范围而不是约1000℃，将金扩散到硅衬底中 根据现有技术。 然后，在从基底上除去剩余的金层之后，将后者再加热至约700℃至约1000℃的较高温度，以激活扩散的金。 在热扩散过程中，由于在金层和硅衬底之间的界面处产生金 - 硅合金区的结果，在降低的温度下的金扩散用于减小衬底的表面不规则性。

公开(公告)号：US4806499A

公开(公告)日：1989-02-21

申请号：US79804

申请日：1987-07-31

申请人： Mamoru Shinohara

发明人： Mamoru Shinohara

IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/22 ,  H01L21/26 ,  H01L21/265

CPC分类号： H01L21/2255 ,  H01L21/8249 ,  Y10S148/009 ,  Y10S148/031 ,  Y10S148/038 ,  Y10S438/92

摘要： The invention relates to a method of manufacturing a Bi-CMOS semiconductor IC device in which the bipolar transistor structure contained therein has a flat PN plane junction between its base and emitter regions, said device having improved breakdown voltage characteristics.The improved method involves preparing a silicon substrate having a P-type base region formed in an N-type collector region, forming a thick silicon oxide layer over the suface of a bipolar transistor region on said substrate, selectively removing the silicon oxide layer to form a first window exposing a part of the collector region and a second window exposing a part of the base region, diffusing phosporus atoms into the base region and collector region through said first and second windows to form an emitter region in the base region and a collector contact in the collector region, subjecting the structure thus-obtained to an oxidation process in a wet oxygen atmosphere at a temperature of 940.degree. C..+-. 20.degree. C. to form a thin silicon oxide layer in the windows, whereby the thin oxide layer on the emitter region invades the emitter region to accomodate the phosphorus atoms, selectively removing a portion of the thin oxide film to form a third window, thereby exposing a surface of the emitter region and subjecting the structure thus-obtained to an impurity drive-in process to rediffuse the phosphorus atoms contained in the remaining thin oxide film into the emitter region, whereby the PN junction plane between the base and emitter regions is flattened. Other variations of this general method are disclosed.

摘要翻译： 本发明涉及一种制造Bi-CMOS半导体IC器件的方法，其中其中包含的双极晶体管结构在其基极和发射极区域之间具有平坦的PN平面结，所述器件具有改进的击穿电压特性。 改进的方法包括制备在N型集电极区域中形成有P型基极区域的硅衬底，在所述衬底上的双极晶体管区域的表面上形成厚的氧化硅层，选择性地去除氧化硅层以形成 暴露部分集电极区域的第一窗口和暴露基部区域的一部分的第二窗口，通过所述第一和第二窗口将磷氧原子扩散到基极区域和集电极区域中，以在基极区域中形成发射极区域，并且收集器 在集电极区域接触，在940℃±20℃的温度下，在湿氧气氛中对由此获得的结构进行氧化处理，以在窗口中形成薄的氧化硅层，由此薄的 发射极区域上的氧化物层侵入发射极区域以容纳磷原子，选择性地去除一部分薄氧化膜以形成第三窗口，从而暴露出第 e发射极区域，并使由此获得的结构进行杂质驱入工艺，将剩余的薄氧化物膜中包含的磷原子重新引入发射极区域，由此基极和发射极区域之间的PN结平面变平。 公开了该通用方法的其它变型。

公开(公告)号：US4624047A

公开(公告)日：1986-11-25

申请号：US659962

申请日：1984-10-11

申请人： Satoru Tani

发明人： Satoru Tani

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/08 ,  H01L27/082 ,  H01L29/73 ,  H01L21/302 ,  H01L21/38

CPC分类号： H01L21/76 ,  H01L21/743 ,  H01L21/76297 ,  H01L21/8222 ,  Y10S148/038 ,  Y10S148/085 ,  Y10S148/135 ,  Y10S438/973

摘要： A method for fabricating isolated regions for a dielectric isolated complementary integrated circuit which avoids the difficulty of mask alignment and patterning on a deeply etched uneven surface of the substrate by aligning the patterns before etching and thereby forming p-type and n-type islands at the same time. A poly-silicon layer is grown on the surface of the substrate covering the islands and the substrate is removed from its back surface, leaving the islands embedded in the poly-silicon layer which becomes a new substrate.

摘要翻译： 一种用于制造绝缘隔离互补集成电路的隔离区域的方法，其通过在蚀刻之前对准图案并由此在其上形成p型和n型岛而避免了掩模对准和图案化在衬底的深蚀刻不平坦表面上的困难 同时。 在覆盖岛的衬底的表面上生长多晶硅层，并且将衬底从其背表面去除，从而将岛嵌入到成为新衬底的多晶硅层中。

公开(公告)号：US3808473A

公开(公告)日：1974-04-30

申请号：US17786271

申请日：1971-09-03

申请人： MATSUSHITA ELECTRIC IND CO LTD

发明人： YAMASHITA A ,  TANAKA M ,  TSUZAKI T

IPC分类号： H01L21/00 ,  H01L27/00 ,  H01L27/07 ,  H04R23/00 ,  H01L11/00 ,  H01L15/00

CPC分类号： H04R23/006 ,  H01L21/00 ,  H01L27/00 ,  H01L27/0788 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/085

摘要： A semiconductor device comprised by assembling a part having a mechano-electrical converting function comprising a metalsemiconductor contact provided in parallel or substantially parallel with a junction of a semiconductor body and a part of electrical circuit comprising such elements as a transistor, diode, resistor, inductor or capacitor into the semiconductor body.

摘要翻译： 一种半导体器件，包括组装具有机电转换功能的部件，该功能包括与半导体主体和电路的一部分并联或大致平行地设置的金属半导体触点，该电路包括诸如晶体管，二极管，电阻器 ，电感器或电容器进入半导体体。

公开(公告)号：US3725145A

公开(公告)日：1973-04-03

申请号：US3725145D

申请日：1970-03-27

申请人： HITACHI LTD

发明人： MAKI M

IPC分类号： H01L21/761 ,  H01L21/00 ,  H01L21/22 ,  H01L21/331 ,  H01L21/82 ,  H01L27/02 ,  H01L27/06 ,  H01L29/00 ,  H01L29/73 ,  H01L7/44

CPC分类号： H01L21/00 ,  H01L21/82 ,  H01L27/0255 ,  H01L27/0635 ,  H01L29/00 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/04 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/097 ,  Y10S148/151 ,  Y10S252/95

摘要： SEMICONDUCTOR DEVICES CONTAINING TWO DIFFUSED REGIONS WITH DIFFERENT DEPTHS FORMED IN A COMMON SEMICONDUCTOR SUBSTRATE ARE MADE BY, FOR EXAMPLE, FIRST SELECTIVELY DIFFUSING GERMANIUM INTO THE SURFACE OF AN N-TYPE SILICON CRYSTALLINE SUBSTRATE AND, THEREAFTER, SELECTIVELY DIFFUSING BORON INTO THE REGION CONTAINING THEN DIFFUSED GERMANIUM AS WELL AS INTO ANOTHER SURFACE PORTION OF THE SUBSTRATE WHERE THE GERMANIUM HAS NOT BEEN DIFUSED.

公开(公告)号：US3594241A

公开(公告)日：1971-07-20

申请号：US3594241D

申请日：1968-01-11

申请人： TEKTRONIX INC

发明人： BRESEE HEBER J

IPC分类号： H01L29/73 ,  H01L21/00 ,  H01L21/22 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L7/34

CPC分类号： H01L27/0635 ,  H01L21/00 ,  H01L21/82 ,  H01L21/8248 ,  H01L21/8249 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/151

摘要： A MONOLITHIC INTEGRATED CIRCUIT A PLURALITY OF FIELD EFFECT TRANSISTORS AND BIPOLAR TRANSISTORS FORMED IN A SINGLE EPITAXIAL LAYER ON THE SAME SEMICONDUCTOR MEMBER AND A METHOD FOR DOING SO WITH DIFFUSION STEPS COMMON TO BOTH TYPES OF TRANSISTORS, ARE DESCRIBED. THE TOP GATE OF A PN JUNCTION GATED FIELD EFFECT TRANSISTOR AND THE EMITTER OF AN NPN BIPOLAR TRANSISTOR ARE FORMED SIMULTANEOUSLY, WHILE THE SOURCE AND DRAIN OF THE FIELD EFFECT TRANSISTOR AND THE BASE OF THE BIPOLAR TRANSISTOR ARE FORMED SIMULTANEOUSLY. THE CHANNEL PORTIN OF THE FIELD EFFECT TRANSISTOR IS FORMED SEPARATELY WITH A DOPING IMPURITY CONCENTRATION OF LOWER SURFACE VALUE AND LOWER SLOPE THAN ANY OF THE OTHER ELEMENTS TO PROVIDE SUCH CHANNEL WITH A HIGH RESISTANCE WHICH IT MORE UNIFORM AND EASIER TO REPRODUCE.