公开(公告)号：US09652804B2

公开(公告)日：2017-05-16

申请号：US14134688

申请日：2013-12-19

Applicant: Chicago Mercantile Exchange Inc.

Inventor： Zachary Bonig ,  Haifeng Zheng ,  Don Mendelson ,  Mike Donaghy ,  Akrapong Lin

IPC: G06Q40/04 ,  H04L12/833 ,  H04L12/859 ,  H04L12/801 ,  H04L12/863

CPC classification number: G06Q40/04 ,  H04L12/66 ,  H04L47/2475 ,  H04L47/28 ,  H04L47/31 ,  H04L47/34 ,  H04L47/621 ,  H04L47/6225 ,  H04L47/6275 ,  H04L49/9036 ,  H04L49/9042 ,  H04L69/16

Abstract: Methods, devices, and systems for facilitation of deterministic management of a plurality of electronic message packets communicated to an application via a network from a plurality of message sources. The facilitation involves receiving each of the plurality of electronic message packets from the network, determining an order in which each electronic message packet was received relative to the reception of others of the plurality of electronic message packets, and providing the order to the application.

公开(公告)号：US20160239439A1

公开(公告)日：2016-08-18

申请号：US15135479

申请日：2016-04-21

Applicant: MediaTek Inc.

Inventor： Kuo-Cheng Lu

IPC: G06F13/16 ,  H04L12/861 ,  H04L5/22

CPC classification number: G06F13/1647 ,  G06F13/1663 ,  H04L5/22 ,  H04L49/9036 ,  Y02D10/14

Abstract: Methods and apparatuses regarding shared buffer arbitration for packet-based switching are described. A data packet may be received by a packet buffer including a first plurality of banks of memory units and a second plurality of banks of memory units. Each memory unit may store one cell of data and accommodate one access operation in one clock cycle. In an event that the data packet includes at least two cells of data, the at least two cells of the data packet may be alternately written into at least one memory unit in the first plurality of banks of memory units and at least one memory unit in the second plurality of banks of memory units. Cells of data packets may be read from the first plurality of banks of memory units and the second plurality of banks of memory units according to a time-division multiplexing (TDM) scheme.

Abstract translation: 描述了关于基于分组交换的共享缓冲器仲裁的方法和装置。 数据分组可以由包括第一多个存储单元组和第二多个存储单元组的分组缓冲器接收。 每个存储器单元可以存储一个数据单元并且在一个时钟周期内容纳一个存取操作。 在数据分组包括至少两个数据单元的情况下，数据分组的至少两个单元可以被交替地写入到第一多个存储单元组中的至少一个存储器单元中，并且至少一个存储器单元 第二组多个存储单元。 可以根据时分复用（TDM）方案从存储器单元的第一多个存储体单元和第二多个存储器单元组读取数据分组的单元。

公开(公告)号：US09178839B2

公开(公告)日：2015-11-03

申请号：US12179242

申请日：2008-07-24

Applicant: Omar Cardona ,  James B. Cunningham ,  Baltazar De Leon, III ,  Jeffrey P. Messing

Inventor： Omar Cardona ,  James B. Cunningham ,  Baltazar De Leon, III ,  Jeffrey P. Messing

IPC: H04L12/861 ,  H04L12/891

CPC classification number: H04L49/9036 ,  H04L47/41 ,  H04L49/90 ,  Y02D50/30

Abstract: In link aggregation configurations, a data packet may be copied into a buffer space of a first NIC. Load balancing techniques may determine that the packet should be transmitted by a second NIC. The packet exists in memory that the second NIC cannot access. The data packet is copied into memory accessible to the second NIC or the memory location of the packet is registered with the NIC. A copy penalty is incurred if a packet is copied from a first buffer space to a second buffer space. A registration penalty is incurred if the location within the first buffer space is registered with the second NIC. Functionality can be implemented within a link aggregation configuration to register buffer space shared among interconnected NICs. Sharing of buffer space between interconnected NICs allows any one of the NICs to access data within the shared buffer space without incurring a penalty.

Abstract translation: 在链路聚合配置中，可以将数据分组复制到第一NIC的缓冲空间中。 负载均衡技术可以确定分组应该由第二NIC发送。 数据包存在于第二个NIC无法访问的内存中。 将数据包复制到第二个NIC可访问的存储器中，或者将该数据包的存储位置注册到NIC。 如果将数据包从第一个缓冲区复制到第二个缓冲区，则会产生复制损失。 如果第一个缓冲空间内的位置与第二个NIC进行了注册，就会产生注册损失。 可以在链路聚合配置中实现功能，以注册在互连NIC之间共享的缓冲区空间。 在互连NIC之间共享缓冲区空间允许任何一个NIC访问共享缓冲区空间内的数据，而不会造成惩罚。

公开(公告)号：US09094231B2

公开(公告)日：2015-07-28

申请号：US13893796

申请日：2013-05-14

Applicant: Panasonic Corporation

Inventor： Atsushi Yoshida ,  Tomoki Ishii ,  Takao Yamaguchi

IPC: H04L12/40 ,  H04L12/861

CPC classification number: H04L12/4015 ,  H04L49/9036 ,  H04L49/9047

Abstract: The router is used to relay a packet to be transmitted from one node to another in an integrated circuit that has distributed buses according to a packet exchange method. The router includes: a plurality of buffers, each of which configured to store packets with information indicating their transmission node; a classifying section configured to classify the buffers that store the packets into a number of groups according to the transmission nodes of the packets; a selecting section configured to select at least one of the buffers of each group; and an output port configured to sequentially output the packets that are stored in the selected buffer.

Abstract translation: 该路由器用于在具有根据分组交换方法的分布式总线的集成电路中中继要从一个节点发送到另一节点的分组。 路由器包括：多个缓冲器，每个缓冲器被配置为存储具有指示其传输节点的信息的分组; 分类单元，被配置为根据分组的传输节点将存储分组的缓冲区分类成多个组; 选择部，被配置为选择每个组中的至少一个缓冲器; 以及输出端口，被配置为顺序地输出存储在所选择的缓冲器中的分组。

公开(公告)号：US08788591B2

公开(公告)日：2014-07-22

申请号：US10794411

申请日：2004-03-04

Applicant: Jianguo Jiang ,  Yaping Liu ,  Jingwei Liang ,  Wei Huang ,  Shijun Wu

Inventor： Jianguo Jiang ,  Yaping Liu ,  Jingwei Liang ,  Wei Huang ,  Shijun Wu

IPC: G06F15/16

CPC classification number: H04L51/26 ,  G06F9/546 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/521 ,  H04L47/6215 ,  H04L49/90 ,  H04L49/9036 ,  H04L51/14 ,  H04L51/30

Abstract: Messages are received and retained in memory and are batch processed including transferring the messages to a cell pool having cells of predetermined size. The location and size of the messages are recorded in a table map with other pertinent information as is required. Messages in the cell pool are processed and delivered asynchronously.

Abstract translation: 消息被接收并保留在存储器中并被批处理，包括将消息传送到具有预定大小的小区的小区池。 消息的位置和大小记录在表格映射中，并且需要其他相关信息。 单元池中的消息将被异步处理和传送。

公开(公告)号：US08687639B2

公开(公告)日：2014-04-01

申请号：US12478652

申请日：2009-06-04

Applicant: Ambuj Kumar

Inventor： Ambuj Kumar

IPC: H04L12/28

CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9036 ,  H04L49/9057

Abstract: A system for ordering packets. The system includes a first memory, e.g., FIFO, storing transition information for posted packets, e.g., 1 when a posted packet transitions from a non-posted packet and 0 otherwise. A second memory stores transition information for non-posted packets, e.g., 1 when a non-posted packet transitions from a posted packet and 0 otherwise. A counter increments responsive to detecting a transition in the first memory and decrements responsive to detecting a transition in the second memory. A controller orders a posted packet for transmission prior to a non-posted packet if a value of the counter is negative and when a transitional value associated with the non-posted packet is 1, and wherein the controller orders either a posted packet or a non-posted packet otherwise. The first and the second memory may be within a same memory component.

Abstract translation: 用于排序数据包的系统 该系统包括第一存储器，例如FIFO，存储用于发布的分组的转换信息，例如当发布的分组从非发布的分组转变时为1，否则为0。 第二存储器存储用于未发布的分组的转换信息，例如当非发布分组从发布的分组转变时为1，否则为0。 响应于检测到第一存储器中的转变而响应于检测到第二存储器中的转变而递减的计数器递增。 如果计数器的值为负并且与非发布的分组相关联的过渡值为1，则控制器在未发布的分组之前命令发布的分组进行传输，并且其中控制器命令发布的分组或非分组的分组 否则的话。 第一和第二存储器可以在相同的存储器组件内。

公开(公告)号：US08665725B2

公开(公告)日：2014-03-04

申请号：US13523994

申请日：2012-06-15

Applicant: Bruce Kwan ,  Puneet Agarwal

Inventor： Bruce Kwan ,  Puneet Agarwal

IPC: H04L12/28 ,  H04L12/56 ,  G06F3/00 ,  G06F5/00

CPC classification number: H04L49/9005 ,  H04L47/6215 ,  H04L49/9036

Abstract: A system and method for hierarchical adaptive dynamic egress port and queue buffer management. Efficient utilization of buffering resources in a commodity shared memory buffer switch is key to minimizing packet loss. Efficient utilization of buffering resources is enabled through adaptive queue limits that are derived from an adaptive port limit.

Abstract translation: 一种用于分层自适应动态出口端口和队列缓冲区管理的系统和方法。 在商品共享内存缓冲交换机中高效利用缓冲资源是最大限度地减少数据包丢失的关键。 通过从自适应端口限制导出的自适应队列限制，能够有效利用缓冲资源。

公开(公告)号：US08312241B2

公开(公告)日：2012-11-13

申请号：US12043943

申请日：2008-03-06

Applicant: Chi-Lie Wang ,  Jason Z. Mo

Inventor： Chi-Lie Wang ,  Jason Z. Mo

IPC: G06F12/12

CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9036

Abstract: Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.

Abstract translation: 在串行缓冲器中，请求数据包被写入存储器缓冲器的可用存储器块，这些存储器块由空闲缓冲器指针列表标识。 当请求数据包被写入存储器块时，存储块从空闲缓冲区指针列表中移除，并被添加到使用的缓冲区指针列表中。 读取所使用的缓冲器指针列表中的存储器块，从而从串行缓冲器发送关联的请求包。 当从存储器块读取请求数据包时，从使用的缓冲区指针列表中删除存储器块，并将其添加到请求缓冲区指针列表中。 如果在超时时段内接收到相应的响应包，则将该存储器块从请求缓冲区指针列表传送到空闲缓冲区指针列表。 否则，内存块从请求缓冲区指针列表传输到使用的缓冲区指针列表。

公开(公告)号：US08275903B1

公开(公告)日：2012-09-25

申请号：US13111475

申请日：2011-05-19

Applicant: Fengyan Shao ,  Shashank J. Pandhare ,  Ying Ping Lok

Inventor： Fengyan Shao ,  Shashank J. Pandhare ,  Ying Ping Lok

IPC: G06F15/16

CPC classification number: H04L49/9089 ,  G06F9/5016 ,  G06F9/544 ,  H04L49/9031 ,  H04L49/9036 ,  H04L49/9063

Abstract: A method and system for concurrent processing transmit requests uses transmit queue including a circular buffer and a queue state including a producer index, a consumer index, and a producer list. Producer processes write to the circular buffer concurrently. The producer list signals which portion of the circular buffer are allocated to each of the producer processes.

Abstract translation: 用于并发处理发送请求的方法和系统使用包括循环缓冲器和包括生产者索引，消费者索引和生产者列表的队列状态的发送队列。 生产者流程同时写入循环缓冲区。 生成器列表将循环缓冲器的哪个部分分配给每个生成器处理。

公开(公告)号：US20120170472A1

公开(公告)日：2012-07-05

申请号：US12983104

申请日：2010-12-31

Applicant: EDMUND CHEN ,  RAMANATHAN LAKSHMIKANTHAN ,  RANJIT ROZARIO ,  BRIAN ALLEYNE ,  STEPHEN CHOW ,  PATRICK WANG ,  EDWARD HO ,  THOMAS YIP ,  SUN DEN CHEN ,  MICHAEL FENG

Inventor： EDMUND CHEN ,  RAMANATHAN LAKSHMIKANTHAN ,  RANJIT ROZARIO ,  BRIAN ALLEYNE ,  STEPHEN CHOW ,  PATRICK WANG ,  EDWARD HO ,  THOMAS YIP ,  SUN DEN CHEN ,  MICHAEL FENG

IPC: H04L12/56 ,  H04L12/26

CPC classification number: H04L49/9073 ,  H04L47/12 ,  H04L47/2441 ,  H04L47/32 ,  H04L49/9036 ,  H04L49/9063 ,  H04L49/9078

Abstract: Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.

Abstract translation: 本发明的实施例包括一种在分组处理期间避免存储器带宽利用的方法。 分组处理核心接收多个分组。 分组处理核心识别分组的服务质量（QoS）描述符。 分组处理核心确定至少一个分组应该被移动到在分组被发送到出口端口之前存储的片外分组。 分组处理核心基于至少部分地确定分组的QoS描述符。 分组处理核心将确定的分组移动到片外分组存储。 分组处理核心在分组被发送到出口端口之前确定至少一个分组不应该被移动到片外分组存储。 该决定至少部分地基于分组的QoS描述符进行。