知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

34 records (took 0.021 seconds)

筛选除外

    Method and apparatus for congestion and fault management with time-to-live
    1.
    发明授权
    Method and apparatus for congestion and fault management with time-to-live 有权
    拥挤和故障管理的方法和装置与生存时间

    公开(公告)号：US08902765B1

    公开(公告)日：2014-12-02

    申请号：US12712560

    申请日：2010-02-25

    Applicant: Chi-Lie Wang ,  Jason Z Mo

    Inventor： Chi-Lie Wang ,  Jason Z Mo

    IPC: G01R31/08 ,  H04L12/841

    CPC classification number: H04L47/286 ,  H04L47/10 ,  H04L47/32 ,  H04L49/3045 ,  H04L49/901

    Abstract: A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.

    Abstract translation: 已经公开了具有生存时间（TTL）的拥塞和故障管理的方法和装置。 每次将数据包传输到出口端口的最终缓冲区时，相关的TTL超时计数器将加载一个值。 如果在TTL超时之前数据包不能从出口端口传出，则通过从对应的虚拟输出队列（VOQ）条目中删除内存缓冲区指针来清除该数据包。

    Partial packet write and write data filtering in a multi-queue first-in first-out memory system
    4.
    发明授权
    Partial packet write and write data filtering in a multi-queue first-in first-out memory system 有权
    在多队列先进先出存储器系统中部分数据包写入和写入数据过滤

    公开(公告)号：US07805552B2

    公开(公告)日：2010-09-28

    申请号：US11040896

    申请日：2005-01-21

    Applicant: Mario Au ,  Jason Z. Mo ,  Hui Su

    Inventor： Mario Au ,  Jason Z. Mo ,  Hui Su

    IPC: G06F13/00 ,  G06F3/00 ,  G06F5/00

    CPC classification number: G06F5/065 ,  G06F2205/108

    Abstract: A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packet write and partial packet read operations, such that a queue switch can be performed in the middle of packet write or packet read operations. The packet status bit also enables data filtering to be performed between an activated EOP marker and a subsequently received SOP marker (i.e., between the end of one packet and the start of the next packet). Packet mark and re-write and packet mark and re-read operations are also enabled.

    Abstract translation: 多队列存储器系统被配置为以分组模式操作。 每个分组包括SOP（分组开始）标记和EOP（分组结束）标记。 分组状态位（PSB）用于实现分组模式。 分组状态位使得能够进行部分分组写入和部分分组读取操作，使得可以在分组写入或分组读取操作的中间执行队列切换。 分组状态位还使得能够在激活的EOP标记和随后接收的SOP标记（即，在一个分组的结束和下一个分组的开始之间）之间执行数据过滤。 数据包标记和重写以及数据包标记和重新读取操作也被启用。

    Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system
    6.
    发明授权
    Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system 有权
    多个计数器可以缓解多队列先进先出的内存系统中的标志限制

    公开(公告)号：US07870310B2

    公开(公告)日：2011-01-11

    申请号：US11040892

    申请日：2005-01-21

    Applicant: Mario Au ,  Jason Z. Mo

    Inventor： Mario Au ,  Jason Z. Mo

    IPC: G06F13/28 ,  G11C7/00 ,  G06F7/38

    CPC classification number: G06F5/065 ,  G06F5/14 ,  G11C8/16

    Abstract: A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.

    Abstract translation: 一种操作多队列设备的方法，包括：（1）存储多个读取（写入）计数指针，其中读取（写入）计数指针中的每一个与多队列设备的相应队列相关联（ 2）提供与当前队列相关联的读取（写入）计数指针以读取（写入）标志逻辑，（3）响应于由每个读取（写入）操作执行的每个读取（写入）操作，调整与当前队列相关联的读取（写入）计数指针 （4）指示从当前队列到下一队列的读（写）队列切换，（5）检索与下一队列相关联的读（写）计数指针; 然后（6）同时将与当前队列相关联的读（写）计数指针和与下一队列相关联的读（写）计数指针提供给读（写）标志逻辑。

    Method To Support Flexible Data Transport On Serial Protocols
    7.
    发明申请
    Method To Support Flexible Data Transport On Serial Protocols 有权
    在串行协议上支持灵活数据传输的方法

    公开(公告)号：US20090225769A1

    公开(公告)日：2009-09-10

    申请号：US12043918

    申请日：2008-03-06

    Applicant: Chi-Lie Wang ,  Jason Z. Mo

    Inventor： Chi-Lie Wang ,  Jason Z. Mo

    IPC: H04L12/56

    CPC classification number: H04L49/9042 ,  H04L49/90

    Abstract: A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the selected queue. The serial buffer also transfers out packets as a bus master when a water level exceeds a water mark within a queue. The serial buffer constructs packet headers for these bus master transfers, which may be performed in a flush mode or a non-flush mode (in packet mode), or in a flush mode (in raw data mode).

    Abstract translation: 串行缓冲区通过能够以分组模式或原始数据模式运行的队列来传输分组。 在分组模式下，整个分组存储在队列中。 在原始数据模式下，报文头/分隔符信息不存储在队列中（仅存储数据包数据）。 响应于从机读请求，可将数据包传送出队列。 串行缓冲器构成响应于从读取请求的分组报头，并且从所选队列中检索指定数量的分组数据。 当水位超过队列内的水位时，串行缓冲器还将数据包作为总线主机传输。 串行缓冲区构建这些总线主机传输的数据包头，可以以冲洗模式或非冲洗模式（分组模式）或冲洗模式（原始数据模式）执行。

    Method And Structure To Support System Resource Access Of A Serial Device Implementing A Lite-Weight Protocol
    8.
    发明申请
    Method And Structure To Support System Resource Access Of A Serial Device Implementing A Lite-Weight Protocol 有权
    支持系统资源访问的方法和结构实现一个轻量级协议的串行设备

    公开(公告)号：US20080205422A1

    公开(公告)日：2008-08-28

    申请号：US11679817

    申请日：2007-02-27

    Applicant: Chi-Lie Wang ,  Jason Z. Mo ,  Calvin Nguyen

    Inventor： Chi-Lie Wang ,  Jason Z. Mo ,  Calvin Nguyen

    IPC: H04L12/56

    CPC classification number: H04L49/9089 ,  H04L47/2483 ,  H04L49/90 ,  H04L49/901

    Abstract: On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow through the serial buffer with the maximum bandwidth supported by the serial interface. The Lite-weight protocol also supports read accesses to queues of the serial buffer (which reside on the normal data packet path). The Lite-weight protocol also supports doorbell commands for status/error reporting.

    Abstract translation: 使用Lite-weight协议的优先级数据包访问串行缓冲区的片上资源。 在串行缓冲器上提供优先级分组路径，以支持优先级分组。 正常数据包在正常的数据包路径上进行处理，该路径与优先包路径并行运行。 串行缓冲区的系统资源可以根据优先级分组进行访问，而不会阻塞正常数据包的流量。 因此，正常数据包可以通过串行接口支持的最大带宽流经串行缓冲器。 Lite-weight协议还支持对串行缓冲区（驻留在正常数据包路径）的队列的读访问。 Lite-weight协议还支持用于状态/错误报告的门铃命令。

    Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system
    9.
    发明授权
    Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system 有权
    在多队列先进先出存储器系统中，状态总线仅在循环模式操作期间仅访问可用象限

    公开(公告)号：US07269700B2

    公开(公告)日：2007-09-11

    申请号：US11040893

    申请日：2005-01-21

    Applicant: Mario Au ,  Jason Z. Mo ,  Cheng-Han Wu

    Inventor： Mario Au ,  Jason Z. Mo ,  Cheng-Han Wu

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G11C7/10

    CPC classification number: G06F5/065

    Abstract: A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M−(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.

    Abstract translation: 提供了一种用于具有多个队列的多队列存储装置中的标志逻辑电路。 第一级存储器存储多队列存储器设备中的每个队列的标志值。 标志值以下述方式从第一级存储器路由到具有宽度N的标志状态总线。 状态总线控制电路接收识别由多队列存储装置实际使用的队列数M的信号，并且作为响应，生成X个控制值的重复模式，其中X等于（M-（M mod N ））/ N + 1。 响应于X控制值的重复模式，选择器电路将X组N标志值从第一级存储器顺序地路由到标志状态总线。 X组N标志值包括与实际使用的队列相关联的标志值。

    Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system
    10.
    发明授权
    Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system 有权
    多队列地址生成器，用于多队列先进先出内存系统中的起始和结束地址

    公开(公告)号：US08230174B2

    公开(公告)日：2012-07-24

    申请号：US11040926

    申请日：2005-01-21

    Applicant: Mario Au ,  Jason Z. Mo ,  Xiaoping Fang

    Inventor： Mario Au ,  Jason Z. Mo ,  Xiaoping Fang

    IPC: G06F12/00 ,  G06F13/00

    CPC classification number: G06F5/065

    Abstract: A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the contents of the queue number register. The queue size value indicates the amount of memory (e.g., the number of memory blocks) to be included in each of the N queues. The queue size value is provided to a queue start/end address generator, which automatically generates the start and end address associated with each queue in response to the queue size value. These start and end addresses are stored in queue address register files, which enable proper memory read/write and flag counter operations.

    Abstract translation: 提供了使用设备的现有引脚将期望数量的队列（N）加载到队列号寄存器中的多队列FIFO存储器设备。 队列号寄存器被耦合到队列大小查询表（LUT），其响应于队列号寄存器的内容提供队列大小值。 队列大小值指示要包括在每个N个队列中的存储器量（例如，存储器块的数量）。 队列大小值被提供给队列开始/结束地址生成器，其响应于队列大小值自动生成与每个队列相关联的开始和结束地址。 这些开始和结束地址存储在队列地址寄存器文件中，这样可以实现适当的存储器读/写和标志计数器操作。

Patent Agency Ranking