公开(公告)号：US07117287B2

公开(公告)日：2006-10-03

申请号：US10449926

申请日：2003-05-30

申请人： Brian Smith

发明人： Brian Smith

IPC分类号： G06F13/36 ,  G06F12/00

CPC分类号： G06F5/10 ,  G06F7/78 ,  G06F2205/065

摘要： An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data items out of the order in which they were stored in the queue, thus bypassing the latency inherent in retrieving the items from the queue. Control logic maintains write and read pointers indicating locations in the queue for writing and reading data items. The write pointer is incremented upon every data event to the queue, thereby maintaining a history of data that has been written to the queue, which is useful for diagnostic purposes. A history flag is maintained to indicate whether the write pointer has wrapped around the addresses in the queue, indicating whether all data items in the queue are valid for diagnostic purposes.

摘要翻译： 一种用于在诸如服务器，工作站或存储机器的计算机系统的I / O（输入 - 输出）子系统中维护循环FIFO（先入先出）队列的装置和方法。 队列被耦合到旁路电路，用于提供对它们存储在队列中的顺序的数据项的访问，从而绕过从队列检索项目所固有的等待时间。 控制逻辑维护写入和读取指针，指示队列中的位置用于写入和读取数据项。 写入指针在每个数据事件上递增到队列，从而保持写入队列的数据的历史记录，这对于诊断目的是有用的。 维护历史标志以指示写指针是否缠绕在队列中的地址周围，指示队列中的所有数据项是否对于诊断目的是有效的。

公开(公告)号：US20060161607A1

公开(公告)日：2006-07-20

申请号：US11035933

申请日：2005-01-14

申请人： Fred Gustavson ,  John Gunnels

发明人： Fred Gustavson ,  John Gunnels

IPC分类号： G06F15/00

CPC分类号： G06F7/78

摘要： A method and structure for transposing a rectangular matrix A in a computer includes subdividing the rectangular matrix A into one or more square submatrices and executing an in-place transposition for each of the square submatrices Aij.

摘要翻译： 用于在计算机中转置矩形矩阵A的方法和结构包括将矩形矩阵A细分成一个或多个正方形子矩阵，并为每个正方形子矩阵A ij执行就地转置。

公开(公告)号：US20020013864A1

公开(公告)日：2002-01-31

申请号：US09801021

申请日：2001-03-07

发明人： Robert G. Dandrea ,  Danny Chin ,  Jesse S. Lerman ,  Clement G. Taylor ,  James Fredrickson

IPC分类号： G06F013/00

CPC分类号： G06F7/78 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0676 ,  G06F3/0683 ,  G06F3/0689 ,  G06F5/065 ,  H04N21/2326

摘要： A queuing architecture and method for scheduling disk drive access requests in a video server. The queuing architecture employs a controlled admission policy that determines how a new user is assigned to a specific disk drive in a disk drive array.

摘要翻译： 用于在视频服务器中调度磁盘驱动器访问请求的排队架构和方法。 排队架构采用受控进入策略，确定新用户如何分配给磁盘驱动器阵列中的特定磁盘驱动器。

公开(公告)号：US5375092A

公开(公告)日：1994-12-20

申请号：US73302

申请日：1993-06-08

申请人： Masaharu Taniguchi ,  Tsuyoshi Etoh ,  Manabu Miura

发明人： Masaharu Taniguchi ,  Tsuyoshi Etoh ,  Manabu Miura

IPC分类号： G11C7/00 ,  G06F5/10 ,  G06F7/78 ,  H01L27/10

CPC分类号： G06F7/78 ,  G06F5/10

摘要： In order to enable enlargement/reduction of data with a simple structure in a first-in first-out memory device thereby reducing the circuit scale of this device, output terminals (Q.sub.0 to Q.sub.3) of a read clock counter (16) are shifted to low order digits and connected to input terminals (A.sub.0 to A.sub.2) of a read address decoder (18). The read clock counter (16) and a read data sense amplifier (19) operate in response to read clocks (RK2). Enlarged read data (RD) are outputted from the read data sense amplifier (19). It is possible to implement enlargement/reduction of data by changing connection between the read clock counter (16) and the read address decoder (18), thereby remarkably simplifying the circuit structure of the first-in first-out memory device having an enlargement/reduction function.

摘要翻译： 为了能够在先进先出存储器件中以简单的结构实现数据的放大/缩小，从而减小了该器件的电路规模，读时钟计数器（16）的输出端（Q0至Q3）被转移到 低位数字并连接到读地址解码器（18）的输入端（A0至A2）。 读时钟计数器（16）和读数据读出放大器（19）响应于读时钟（RK2）而工作。 从读取数据读出放大器（19）输出放大的读取数据（RD）。 可以通过改变读时钟计数器（16）和读地址解码器（18）之间的连接来实现数据的放大/缩小，从而显着地简化了具有放大/缩小的先进先出存储器件的电路结构， 还原功能。

公开(公告)号：US5193203A

公开(公告)日：1993-03-09

申请号：US546113

申请日：1990-07-02

申请人： Alain Artieri

发明人： Alain Artieri

IPC分类号： H04N7/167 ,  G06F7/78 ,  G06T1/00

CPC分类号： G06F7/78

摘要： A data shuffler of the pipeline type receives successive trains of n sequential data words and rearranges data words in each train according to a predetermined order. It comprises p (p.ltoreq.n) elementary processing units arranged in series. Each unit comprises an input, an output, a one-word storage register (20), a steering means (21) in order, in response to a binary control, to connect the input to the output either directly or through the register; and means for periodically supplying to each of the p steering means a sequence of n control bits determined as a function of said predetermined order.

摘要翻译： 管线类型的数据洗牌器接收n个连续数据字的连续列，并根据预定顺序重排每个列中的数据字。 它包括串联布置的p（p

公开(公告)号：US5101202A

公开(公告)日：1992-03-31

申请号：US645875

申请日：1991-01-25

申请人： Phillipe Chaisemartin ,  Alain Artieri

发明人： Phillipe Chaisemartin ,  Alain Artieri

IPC分类号： G06F7/78 ,  H03M9/00

CPC分类号： G06F7/78 ,  H03M9/00

摘要： A serializer/deserializer for a flow of n-bits of data shifted according to the rate of a clock includes an n-rows and n-columns matrix of 1-bit registers (00-77). Each 1-bit register is connected through its input to a first switch connected to the output of the register in the same row and lower rank column and to a second switch connected to the output of the register in the same column and upper rank row. Input terminals (E0-E7) are connected to the registers of the lower rank column and of the upper rank row. Output terminals (S0-S7) are connected to the registers of the upper rank column and of the lower rank row. The matrix cells are arranged according to a triangle, the cells being arranged one with respect to the other according to the structural corresponding to folding a square matrix along its diagonal.

摘要翻译： 用于根据时钟速率移位的n位数据流的串行器/解串器包括1位寄存器（00-77）的n行和n列矩阵。 每个1位寄存器通过其输入连接到连接到同一行和低级列中的寄存器的输出的第一开关和连接到同一列和高级列中的寄存器的输出的第二开关。 输入端子（E0-E7）连接到下排列和上排列的寄存器。 输出端子（S0-S7）连接到上排列和下排列的寄存器。 矩阵单元根据三角形布置，根据对应于沿其对角线折叠正方形矩阵的结构，单元相对于另一个布置一个单元。

公开(公告)号：US4918644A

公开(公告)日：1990-04-17

申请号：US868291

申请日：1986-05-28

申请人： Hiroaki Terada ,  Katushiko Asada ,  Hiroaki Nishikawa ,  Souichi Miyata ,  Satoshi Matsumoto ,  Hajime Asano ,  Masahisa Shimizu ,  Hiroki Miura ,  Kenji Shima ,  Shinji Komori

发明人： Hiroaki Terada ,  Katushiko Asada ,  Hiroaki Nishikawa ,  Souichi Miyata ,  Satoshi Matsumoto ,  Hajime Asano ,  Masahisa Shimizu ,  Hiroki Miura ,  Kenji Shima ,  Shinji Komori

IPC分类号： G06F7/78

CPC分类号： G06F7/78

摘要： A data processing apparatus includes two data transmission paths formed likewise in a loop fashion. These data transmission paths include a plurality of latch registers connected in a cascade fashion respectively and are constituted as a so-called self-running type shift register wherein each data word constituting a data packet is shifted in sequence provided that a pre-stage register is vacant. Data packets are transmitted in the directions reverse to each other on the two loop-shaped data transmission paths an identification data included in each data packet being transmitted is detected in a section defined as a data packet pair detecting section. The detected identification data are compared in a comparing circuit and, one new data packet is produced from the two data packets in a manner that a data packet is joined from one data transmission path to the other data transmission path.

摘要翻译： 数据处理装置包括以循环方式同样形成的两个数据传输路径。 这些数据传输路径分别包括以级联方式连接的多个锁存寄存器，并且被构成为所谓的自运行型移位寄存器，其中构成数据包的每个数据字按顺序移位，前提是前级寄存器是 空的。 数据分组在两个环形数据传输路径上沿相反的方向发送，在被定义为数据分组对检测部分的部分中检测到正在发送的每个数据分组中包括的标识数据。 检测到的识别数据在比较电路中进行比较，并且以数据分组从一个数据传输路径连接到另一个数据传输路径的方式从两个数据分组产生一个新的数据分组。

公开(公告)号：US4864544A

公开(公告)日：1989-09-05

申请号：US272563

申请日：1988-11-17

申请人： Michael E. Spak ,  Craig S. Tyl ,  Philip C. Wottrich

发明人： Michael E. Spak ,  Craig S. Tyl ,  Philip C. Wottrich

IPC分类号： G06F7/78 ,  G11C11/412 ,  G11C19/00 ,  G11C19/28

CPC分类号： G06F7/78 ,  G11C11/412 ,  G11C19/00 ,  G11C19/28

摘要： A memory cell is comprised of a cross-coupled master latch and a cross-coupled slave latch. The memory cell includes means for switching on and off power supplies connected to the master latch and the slave latch so as to control the direction of shift in a bidirectional shift. Data is shifted in a first direction when the power supply connected to the master latch is switched off, and data is shifted in a second direction when the power supply connected to the slave latch is switched off.

摘要翻译： 存储器单元由交叉耦合主锁存器和交叉耦合从锁存器组成。 存储单元包括用于接通和断开连接到主锁存器和从锁存器的电源的装置，以便控制双向移位中的移位方向。 当连接到主​​锁存器的电源被关闭时，数据沿着第一方向移位，并且当连接到从锁存器的电源被关闭时，数据沿第二方向移位。

公开(公告)号：US4813015A

公开(公告)日：1989-03-14

申请号：US838993

申请日：1986-03-12

申请人： Michael E. Spak ,  Craig S. Tyl ,  Philip C. Wottrich

发明人： Michael E. Spak ,  Craig S. Tyl ,  Philip C. Wottrich

IPC分类号： G11C7/00 ,  G06F7/78 ,  G11C11/412 ,  G11C19/00 ,  G11C19/28 ,  G11C8/00

CPC分类号： G06F7/78 ,  G11C11/412 ,  G11C19/00 ,  G11C19/28

摘要： A fracturable x-y random access memory array for performing pushing and popping of data and fracturing the array simultaneously at a common address includes a row fracture circuit responsive to row addresses to fracture the array in the Y-direction and a column fracture circuit responsive to column addresses for fracturing the array in the X-direction. A plurality of memory cells are stacked in a plurality of columns to form an x-y organization which can be randomly accessed in response to the row and column addresses. The memory cells are responsive to a shift control driver circuit for bidirectional shifting of data by either pushing data into or popping data from at any point within one of the plurality of randomly addressable column at the same row and column addresses used to fracture the array defining a fracture point. Data in all of the memory cells in the array with addresses higher (or lower) than the fracture point shift and the memory cells with addresses lower (or higher) than the fracture point maintain their data unchanged.

摘要翻译： 用于执行数据的推动和弹出并且以公共地址同时压裂阵列的可分裂的xy随机存取存储器阵列包括响应于行地址的行断裂电路来使阵列在Y方向上断裂，以及响应于列地址的列断裂电路 用于在X方向上压裂阵列。 多个存储器单元被堆叠在多个列中以形成可以响应于行和列地址而被随机访问的x-y组织。 存储器单元响应于移位控制驱动器电路，用于通过将数据从与多个可随机寻址列中的一个内的任何点处的数据推入或弹出数据进行双向移位，所述相同行和列地址用于破坏定义的数组 骨折点。 阵列中的所有存储单元中的数据，其地址比断裂点位移更高（或更低），并且具有比断裂点更低（或更高）的地址的存储单元保持其数据不变。

公开(公告)号：US4009471A

公开(公告)日：1977-02-22

申请号：US588701

申请日：1975-06-20

申请人： Atsuo Tanaka ,  Koichi Tokura ,  Hiroki Kawahara

发明人： Atsuo Tanaka ,  Koichi Tokura ,  Hiroki Kawahara

IPC分类号： G06F13/14 ,  G06F5/06 ,  G06F7/78 ,  G06F13/00 ,  G11C19/00

CPC分类号： G06F7/78 ,  G06F5/06

摘要： A control unit supplies information and includes a memory for storing information. A data bus connected to the control unit transfers the information. A controlled unit connected to the data bus receives information transferred from the control unit. The controlled unit comprises a plurality of n circuit stages, wherein n is a whole number, connected in tandem. The controlled unit includes first to n.sup.th circuit stages and an i.sup.th circuit stage intermediate the first and n.sup.th circuit stages and designated by the control unit. Information transferred from the control unit is stored in the first circuit stage and is transferred sequentially from the first to the i.sup.th circuit stages. Information stored in the first to (i-1).sup.th circuit stages is transferred to the memory of the control unit via the data bus for storage in the memory when the control unit requires alteration of information stored in the i.sup.th circuit stage. Alternative information is transferred from the control unit to the first circuit stage. The information stored in the memory of the control unit is sequentially transferred to the first circuit stage thereby shifting the alternative information to the i.sup.th circuit stage.

摘要翻译： 控制单元提供信息并且包括用于存储信息的存储器。 连接到控制单元的数据总线传送信息。 连接到数据总线的受控单元接收从控制单元传送的信息。 受控单元包括多个n个电路级，其中n是整数，串联连接。 受控单元包括第一至第n电路级和在第一和第n电路级中间并由控制单元指定的第i个电路级。 从控制单元传送的信息被存储在第一电路级中，并且从第一电路级顺序传送到第i电路级。 存储在第一至第（i-1）个电路级中的信息经由数据总线传送到控制单元的存储器以存储在存储器中，当控制单元需要更改存储在第i个电路级的信息时。 替代信息从控制单元传送到第一电路级。 存储在控制单元的存储器中的信息被顺序地传送到第一电路级，从而将替代信息转移到第i电路级。