公开(公告)号：US12061809B2

公开(公告)日：2024-08-13

申请号：US17949807

申请日：2022-09-21

申请人： Dell Products L.P.

发明人： Dave J. Lindner ,  Mrinalini Chavan

IPC分类号： G06F3/06

CPC分类号： G06F3/0635 ,  G06F3/0613 ,  G06F3/0632 ,  G06F3/067

摘要： Host access to a system DS1 can be configured for a logical device L1 so that L1 is exposed to the host over path P1 from DS1. Prior to configuring host access to L1 on another system DS2, configuration information of DS1 can be updated to include a fully populated uniform host configuration for the host with respect to L1. The fully populated uniform host configuration can identify P1 as well as path P2 between DS2 and the host. Even though P2 may not be established so that L1 is not yet exposed to the host over P2, DS1 can use the information included in the fully populated uniform host configuration to report information to the host regarding path state information for P1 and P2. The host can directly query DS2 regarding P2 in order to determine current up-to-date information regarding the path state of P2 with respect to L1.

公开(公告)号：US20240264834A1

公开(公告)日：2024-08-08

申请号：US18639014

申请日：2024-04-18

申请人： Lodestar Licensing Group, LLC

发明人： Qing Liang ,  Nadav Grosz

IPC分类号： G06F9/30 ,  G06F3/06 ,  G06F9/48 ,  G06F12/1009

CPC分类号： G06F9/30047 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0646 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4806 ,  G06F12/1009 ,  G06F2212/7201

摘要： Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

公开(公告)号：US12056361B2

公开(公告)日：2024-08-06

申请号：US17814888

申请日：2022-07-26

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Wei-Chen Wang ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC分类号： G06F12/00 ,  G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0644 ,  G06F3/0679

摘要： An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

公开(公告)号：US20240256141A1

公开(公告)日：2024-08-01

申请号：US18160603

申请日：2023-01-27

申请人： Dell Products L.P.

发明人： Svetlana Kronrod ,  Vamsi K. Vankamamidi ,  Michael P. Wahl ,  James H. Shimer

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/067

摘要： A method, computer program product, and computing system for receiving one or more IO requests on a storage system coupled to a cloud-based storage platform, wherein the cloud-based storage platform has a defined maximum IOPS rate; determining a current level of utilization of the defined maximum IOPS rate; and determining whether to queue the one or more IO requests for an aggregated write operation to the cloud-based storage platform based, at least in part, upon the current level of utilization of the defined maximum IOPS rate.

公开(公告)号：US12052138B2

公开(公告)日：2024-07-30

申请号：US18195678

申请日：2023-05-10

申请人： Barefoot Networks, Inc.

发明人： Remy Chang

IPC分类号： H04L41/08 ,  G06F1/04 ,  G06F1/20 ,  G06F1/32 ,  G06F1/3234 ,  G06F3/06 ,  G06F13/16 ,  H04L41/0833 ,  H04L45/00 ,  H04L45/745 ,  H04L49/00 ,  H04L49/25 ,  H04L49/40 ,  H04L49/50 ,  H04L49/505 ,  H04L45/64 ,  H04L47/30 ,  H04L69/22

CPC分类号： H04L41/0833 ,  G06F1/04 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3234 ,  G06F3/0613 ,  G06F3/065 ,  G06F3/067 ,  G06F13/161 ,  G06F13/1642 ,  H04L45/38 ,  H04L45/745 ,  H04L49/25 ,  H04L49/3063 ,  H04L49/40 ,  H04L49/501 ,  H04L49/505 ,  H04L45/64 ,  H04L47/30 ,  H04L69/22

摘要： Some embodiments of the invention provide a network forwarding element that can be dynamically reconfigured to adjust its data message processing to stay within a desired operating temperature or power consumption range. In some embodiments, the network forwarding element includes (1) a data-plane forwarding circuit (“data plane”) to process data tuples associated with data messages received by the IC, and (2) a control-plane circuit (“control plane”) for configuring the data plane forwarding circuit. The data plane includes several data processing stages to process the data tuples. The data plane also includes an idle-signal injecting circuit that receives from the control plane configuration data that the control plane generates based on the IC's temperature. Based on the received configuration data, the idle-signal injecting circuit generates idle control signals for the data processing stages. Each stage that receives an idle control signal enters an idle state during which the majority of the components of that stage do not perform any operations, which reduces the power consumed and temperature generated by that stage during its idle state.

公开(公告)号：US12050776B2

公开(公告)日：2024-07-30

申请号：US18049973

申请日：2022-10-26

申请人： Micron Technology, Inc.

发明人： Ying Huang ,  Mark Ish

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

摘要： Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.

公开(公告)号：US20240248609A1

公开(公告)日：2024-07-25

申请号：US18455668

申请日：2023-08-25

申请人： Samsung Electronics Co., Ltd.

发明人： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0683

摘要： An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

公开(公告)号：US20240248606A1

公开(公告)日：2024-07-25

申请号：US18101281

申请日：2023-01-25

申请人： Dell Products L.P.

发明人： Amitai Alkalay ,  Vladimir Shveidel ,  Lior Kamran

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0647 ,  G06F3/067

摘要： Techniques can include: configuring a federation to have a volume as active from only a first storage system so that hosts only sends I/O operations, directed to the first volume, to the first storage system; configuring a second storage system of the federation as inactive with respect to volume; determining, in accordance with criteria, to allow I/O operations directed to the volume to be sent to both the first and second storage systems; transitioning the second storage system, with respect to the volume, from inactive to active; and receiving, from a host at the first and second storage systems, I/O operations directed to the volume while the first and second storage systems are configured as active. The I/O operations can include a first I/O operation received at the second storage system which is redirected, by the second storage system, to the first storage system for servicing.

公开(公告)号：US20240241653A1

公开(公告)日：2024-07-18

申请号：US18126762

申请日：2023-03-27

申请人： Samsung Electronics Co., Ltd.

发明人： Arun GEORGE

IPC分类号： G06F3/06

CPC分类号： G06F3/0631 ,  G06F3/0613 ,  G06F3/067

摘要： The disclosure provides a method, a distributed controller and a system for managing sequential storage devices in a distributed storage environment. The method comprising receiving a client allocation request from a client device and determining at least one zone set from a plurality of zone set based on the client allocation request and predefined I/O parameters. Each zone set of the plurality of zone set comprises a plurality of zones of sequential storage devices. Thereafter, method comprises provisioning the at least one zone set to the client device based on the client allocation request, thereby, managing the sequential storage devices. Each zone of a sequential storage device is arranged into a zone set based on at least one of sequential storage device parameters, and zone parameters. The use of the distributed controller allows optimizing the performance of the sequential storage devices and optimizing the network bandwidth utilization.

公开(公告)号：US20240241645A1

公开(公告)日：2024-07-18

申请号：US18621437

申请日：2024-03-29

申请人： Intel Corporation

发明人： Robert Pawlowski ,  Shruti Sharma ,  Fabio Checconi ,  Sriram Aananthakrishnan ,  Jesmin Jahan Tithi ,  Jordi Wolfson-Pou ,  Joshua B. Fryman

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0656 ,  G06F3/0673

摘要： Systems, apparatuses and methods may provide for technology that includes a plurality of hash management buffers corresponding to a plurality of pipelines, wherein each hash management buffer in the plurality of hash management buffers is adjacent to a pipeline in the plurality of pipelines, and wherein a first hash management buffer is to issue one or more hash packets associated with one or more hash operations on a hash table. The technology may also include a plurality of hash engines corresponding to a plurality of dynamic random access memories (DRAMs), wherein each hash engine in the plurality of hash engines is adjacent to a DRAM in the plurality of DRAMs, and wherein one or more of the hash engines is to initialize a target memory destination associated with the hash table and conduct the one or more hash operations in response to the one or more hash packets.