Checking of the skew constancy of a bit flow
    21.
    发明授权
    Checking of the skew constancy of a bit flow 有权
    检查位流的偏斜常数

    公开(公告)号:US08554813B2

    公开(公告)日:2013-10-08

    申请号:US12852853

    申请日:2010-08-09

    IPC分类号: G06F7/58

    CPC分类号: G06F7/58 G06F7/588 H03K3/84

    摘要: A method and a circuit for detecting a loss in the equiprobable character of a first output bit flow originating from at least one first element of normalization of an initial bit flow, including analyzing the flow rate of the normalization element.

    摘要翻译: 一种用于检测源自起始位流的归一化的至少一个第一元素的第一输出位流的等能特性损失的方法和电路,包括分析归一化元件的流量。

    Bulk-mode resonator having at least partially filled open cavities
    23.
    发明授权
    Bulk-mode resonator having at least partially filled open cavities 有权
    具有至少部分填充的开放空腔的体模式谐振器

    公开(公告)号:US08519806B2

    公开(公告)日:2013-08-27

    申请号:US12794037

    申请日:2010-06-04

    IPC分类号: H03H9/24 H03H9/46 H03H3/013

    摘要: A method for forming a resonator including a resonant element, the resonant element being at least partly formed of a body at least partly formed of a first conductive material, the body including open cavities, this method including the steps of measuring the resonator frequency; and at least partially filling said cavities.

    摘要翻译: 一种用于形成包括谐振元件的谐振器的方法,所述谐振元件至少部分地由至少部分地由第一导电材料形成的主体形成,所述主体包括开放空腔,该方法包括以下步骤:测量谐振器频率; 并且至少部分地填充所述空腔。

    LDPC decoder and method for LDPC decoding based on layered algorithm applied to parity check matrix
    25.
    发明授权
    LDPC decoder and method for LDPC decoding based on layered algorithm applied to parity check matrix 有权
    LDPC解码器和基于分层算法的LDPC解码方法应用于奇偶校验矩阵

    公开(公告)号:US08504892B2

    公开(公告)日:2013-08-06

    申请号:US12760672

    申请日:2010-04-15

    IPC分类号: G06F11/00

    摘要: A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path.

    摘要翻译: 一种低密度奇偶校验解码器,用于基于应用于奇偶校验矩阵的分层算法来执行LDPC解码,所述解码器包括信道存储器,度量存储器,第一和第二操作数提供路径,每个被布置为基于信道值和度量来提供操作数 价值观 处理器块,包括并行的多个处理单元,并且被布置成从第一供应路径接收操作数并确定更新的度量值;缓冲器,被布置成存储来自第一供应路径的操作数中的至少一个; 以及加法器,其耦合到所述处理器块的输出并被布置成通过将所述更新的度量值与所述缓冲器和所述第二供应路径中的所选择的操作数相加来生成更新的通道值。

    Bulk acoustic wave resonator disposed on a substrate having a buried cavity formed therein providing different substrate thicknesses underneath the resonator
    26.
    发明授权
    Bulk acoustic wave resonator disposed on a substrate having a buried cavity formed therein providing different substrate thicknesses underneath the resonator 有权
    放置在其上形成有掩埋腔的衬底上的体声波谐振器提供在谐振器下面的不同衬底厚度

    公开(公告)号:US08456258B2

    公开(公告)日:2013-06-04

    申请号:US12783095

    申请日:2010-05-19

    IPC分类号: H03H9/54

    摘要: A resonant device including a stack of a first metal layer, a piezoelectric material layer, and a second metal layer formed on a silicon substrate, a cavity being formed in depth in the substrate, the thickness of the silicon above the cavity having at least a first value in a first region located opposite to the center of the stack, having a second value in a second region located under the periphery of the stack and having at least a third value in a third region surrounding the second region, the second value being greater than the first and the third values.

    摘要翻译: 一种谐振装置,包括第一金属层,压电材料层和形成在硅衬底上的第二金属层的堆叠,空腔在衬底中深度形成,空腔上方的硅的厚度至少具有 第一值位于与堆叠的中心相对的第一区域中,在位于堆叠的周边下方的第二区域中具有第二值,并且在围绕第二区域的第三区域中具有至少第三值,第二值为 大于第一和第三值。

    Digital predistorter for variable supply amplifier
    27.
    发明授权
    Digital predistorter for variable supply amplifier 有权
    用于可变电源放大器的数字预失真器

    公开(公告)号:US08411792B2

    公开(公告)日:2013-04-02

    申请号:US12849270

    申请日:2010-08-03

    申请人: Vincent Pinon

    发明人: Vincent Pinon

    IPC分类号: H04K1/02

    摘要: An adaptive predistorter for applying a predistortion gain to an input signal to be amplified by a power amplifier having a variable supply voltage, the predistorter including: a predistortion gain block adapted to apply a complex gain to a complex input signal; a first table implemented in a first memory and including a 2-dimensional array of cells storing complex gain values, the first table adapted to output the complex gain values based on an amplitude of the input signal and the value of the variable supply voltage of the power amplifier; and a second table implemented in a second memory and including a 2-dimensional array of cells storing gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output of the power amplifier.

    摘要翻译: 一种用于对要由具有可变电源电压的功率放大器放大的输入信号施加预失真增益的自适应预失真器,所述预失真器包括:适于将复增益应用于复输入信号的预失真增益块; 第一表,其在第一存储器中实现并且包括存储复增益值的单元的二维阵列,所述第一表适于基于输入信号的幅度和可变电源电压的值输出复增益值 功率放大器; 以及第二表,其在第二存储器中实现,并且包括存储用于更新第一表的复数增益值的增益更新值的单元的二维阵列,所述增益更新值是基于功率放大器的输出产生的。

    Analog FIR filter
    29.
    发明授权
    Analog FIR filter 有权
    模拟FIR滤波器

    公开(公告)号:US08369817B2

    公开(公告)日:2013-02-05

    申请号:US12690793

    申请日:2010-01-20

    IPC分类号: H04B1/10

    CPC分类号: H03H15/02 H03H11/1291

    摘要: An analog finite impulse response (AFIR) filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter.

    摘要翻译: 一种模拟有限脉冲响应(AFIR)滤波器,包括至少一个可变跨导块,其具有用于接收输入电压的输入,并且适于在多个连续的至少一个期间顺序地将多个跨导电平中的每一个施加到输入电压 在所述可变跨导块的输出处产生输出电流的所述时间周期,所述至少一个可变跨导块包括多个固定跨导块,每个固定跨导块接收所述输入电压并且能够被独立地激活以提供所述输出电流; 以及耦合到可变跨导块的输出的电容器,以接收输出电流并提供滤波器的输出电压。

    Video detection cell for a set top box
    30.
    发明授权
    Video detection cell for a set top box 有权
    用于机顶盒的视频检测单元

    公开(公告)号:US08346982B2

    公开(公告)日:2013-01-01

    申请号:US11956390

    申请日:2007-12-14

    IPC分类号: G06F3/00 H04N7/16

    摘要: A switch for switching video signals in a set top box between a first interface for connecting the set top box to a television, a second interface for connecting the set top box to a video playback device, and decoding circuitry for decoding a video stream, the set top box including a processor having a low power mode in which the decoding circuitry is inactive, the switch including detection circuitry arranged to detect, while the processor is in the low power mode, activity on a video input line of one of the first and second interfaces, and arranged to output an activation signal to switching circuitry in the switch to activate a loop through between the first and second interfaces when activity is detected.

    摘要翻译: 一种用于在用于将机顶盒连接到电视的第一接口之间的机顶盒中切换视频信号的开关,用于将机顶盒连接到视频回放设备的第二接口以及用于解码视频流的解码电路, 机顶盒包括具有低功率模式的处理器,其中解码电路处于非活动状态,该开关包括检测电路,该检测电路被布置成在处理器处于低功率模式时检测在第一和第二模式之一的视频输入线上的活动 第二接口,并且被布置成将激活信号输出到开关中的开关电路,以在检测到活动时在第一和第二接口之间激活环路。