公开(公告)号：US08921998B2

公开(公告)日：2014-12-30

申请号：US14236236

申请日：2012-08-24

申请人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

发明人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H01L23/10 ,  H01L23/34 ,  H01L23/538 ,  H01L23/373 ,  H01L23/00 ,  H01L25/07 ,  H01L23/498 ,  H01L25/18

CPC分类号： H01L23/5384 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor module has a pair of semiconductor devices, a heat sink, a first electrode, an output electrode and a second electrode. The semiconductor devices are connected in series with each other and have first terminals that are electrically connected to a first power system and a second terminal that is electrically connected to a second power system. The first electrode is electrically connected both to one of the first terminal and to an electrode of one of the semiconductor devices. The output electrode is electrically connected both to the second terminal and to an electrode of the other of the semiconductor device. The second electrode is electrically connected to the other of the first terminals. The second electrode is connected to the heat sink via a first insulating member. The output electrode is connected to the second electrode via a second insulating member.

摘要翻译： 半导体模块具有一对半导体器件，散热器，第一电极，输出电极和第二电极。 半导体器件彼此串联连接并且具有电连接到第一电力系统的第一端子和电连接到第二电力系统的第二端子。 第一电极电连接到第一端子中的一个和半导体器件中的一个的电极。 输出电极与第二端子和半导体器件的另一个的电极电连接。 第二电极与第一端子中的另一个电连接。 第二电极通过第一绝缘构件连接到散热器。 输出电极经由第二绝缘构件与第二电极连接。

公开(公告)号：US08916882B2

公开(公告)日：2014-12-23

申请号：US14116890

申请日：2012-05-11

申请人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

发明人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H03K17/16 ,  H01L27/06 ,  H02M1/08

CPC分类号： H01L27/0629 ,  H01L27/0682 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2924/19105 ,  H02M1/08 ,  H03K17/04123 ,  H03K17/166 ,  H01L2924/00014

摘要： A switching circuit includes: a first switching element (Q1); a resistor (11) inserted between a control electrode (G) of the first switching element (Q1) and a control circuit (13) switching the first switching element (Q1); and a first capacitor (15) and a second switching element (14) connected in series between the control electrode (G) of the first switching element (Q1) and a low potential-side electrode (S) of the first switching element (Q1). A high potential-side electrode of the second switching element (14) is connected to the control electrode (G) of the first switching element (Q1). An electrode of the first capacitor (15) is connected to the low potential-side electrode (S) of the first switching element (Q1). A control electrode of the second switching element (14) is connected to an electrode of the resistor (11) connected to the control circuit (13).

摘要翻译： 开关电路包括：第一开关元件（Q1）; 插入在第一开关元件（Q1）的控制电极（G）和切换第一开关元件（Q1）的控制电路（13）之间的电阻器（11）; 以及串联连接在第一开关元件（Q1）的控制电极（G）和第一开关元件（Q1）的低电位侧电极（S）之间的第一电容器（15）和第二开关元件（14） ）。 第二开关元件（14）的高电位侧电极连接到第一开关元件（Q1）的控制电极（G）。 第一电容器（15）的电极与第一开关元件（Q1）的低电位侧电极（S）连接。 第二开关元件（14）的控制电极连接到与控制电路（13）连接的电阻器（11）的电极。

公开(公告)号：US20140191250A1

公开(公告)日：2014-07-10

申请号：US14234476

申请日：2012-07-27

申请人： Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

发明人： Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H01L23/00 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L29/1602 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K1/206 ,  B23K35/007 ,  B23K35/025 ,  B23K35/282 ,  B23K35/286 ,  B23K2101/34 ,  B23K2101/40 ,  B23K2101/42 ,  C22C18/04 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/29118 ,  H01L2224/32225 ,  H01L2224/83001 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/01322 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.

摘要翻译： 半导体器件的制造方法是通过将半导体元件，至少具有表面的Cu作为主要元素的基板和比半导体元件的形状小的ZnAl焊料芯片进行准位来进行的。 将所述半导体元件和所述基板配置为使得各个接合面彼此面对，并将所述ZnAl共晶焊料夹在所述基板和所述半导体元件之间; 在向ZnAl焊料芯片施加负载的同时，增加夹在基板和半导体元件之间的ZnAl焊料芯片的温度，使得ZnAl焊料芯片熔化形成ZnAl焊料层; 并且在向ZnAl焊料层施加负载的同时降低ZnAl焊料层的温度。

公开(公告)号：US20140159225A1

公开(公告)日：2014-06-12

申请号：US14236236

申请日：2012-08-24

申请人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

发明人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H01L23/538

CPC分类号： H01L23/5384 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor module has a pair of semiconductor devices, a heat sink, a first electrode, an output electrode and a second electrode. The semiconductor devices are connected in series with each other and have first terminals that are electrically connected to a first power system and a second terminal that is electrically connected to a second power system. The first electrode is electrically connected both to one of the first terminal and to an electrode of one of the semiconductor devices. The output electrode is electrically connected both to the second terminal and to an electrode of the other of the semiconductor device. The second electrode is electrically connected to the other of the first terminals. The second electrode is connected to the heat sink via a first insulating member. The output electrode is connected to the second electrode via a second insulating member.

摘要翻译： 半导体模块具有一对半导体器件，散热器，第一电极，输出电极和第二电极。 半导体器件彼此串联连接并且具有电连接到第一电力系统的第一端子和电连接到第二电力系统的第二端子。 第一电极电连接到第一端子中的一个和半导体器件中的一个的电极。 输出电极与第二端子和半导体器件的另一个的电极电连接。 第二电极与第一端子中的另一个电连接。 第二电极通过第一绝缘构件连接到散热器。 输出电极经由第二绝缘构件与第二电极连接。

公开(公告)号：US20140091324A1

公开(公告)日：2014-04-03

申请号：US14116890

申请日：2012-05-11

申请人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

发明人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L27/0682 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2924/19105 ,  H02M1/08 ,  H03K17/04123 ,  H03K17/166 ,  H01L2924/00014

摘要： A switching circuit includes: a first switching element (Q1); a resistor (11) inserted between a control electrode (G) of the first switching element (Q1) and a control circuit (13) switching the first switching element (Q1); and a first capacitor (15) and a second switching element (14) connected in series between the control electrode (G) of the first switching element (Q1) and a low potential-side electrode (S) of the first switching element (Q1). A high potential-side electrode of the second switching element (14) is connected to the control electrode (G) of the first switching element (Q1). An electrode of the first capacitor (15) is connected to the low potential-side electrode (S) of the first switching element (Q1). A control electrode of the second switching element (14) is connected to an electrode of the resistor (11) connected to the control circuit (13).

摘要翻译： 开关电路包括：第一开关元件（Q1）; 插入在第一开关元件（Q1）的控制电极（G）和切换第一开关元件（Q1）的控制电路（13）之间的电阻器（11）; 以及串联连接在第一开关元件（Q1）的控制电极（G）和第一开关元件（Q1）的低电位侧电极（S）之间的第一电容器（15）和第二开关元件（14） ）。 第二开关元件（14）的高电位侧电极连接到第一开关元件（Q1）的控制电极（G）。 第一电容器（15）的电极与第一开关元件（Q1）的低电位侧电极（S）连接。 第二开关元件（14）的控制电极连接到与控制电路（13）连接的电阻器（11）的电极。

公开(公告)号：US08575726B2

公开(公告)日：2013-11-05

申请号：US12073489

申请日：2008-03-06

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01L23/58

CPC分类号： H01L23/142 ,  H01L23/562 ,  H01L24/31 ,  H01L24/83 ,  H01L29/0657 ,  H01L29/32 ,  H01L2224/83801 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor chip including: a first main face having an edge portion, a second main face locating the opposite side to the first main face, a crystalline defect region present within a region including at least the edge portion being adjacent to the first main face, the crystalline defect region being configured to have lower stress than the stress in the other semiconductor region for the same strain; and a metallic substrate to be bonded via a bonding member to the first main face of the semiconductor chip.

摘要翻译： 一种半导体器件，包括：半导体芯片，包括：第一主面，其具有边缘部分，与第一主面相对设置的第二主面，存在于至少包括与第一主面相邻的边缘部分的区域内的晶体缺陷区域 第一主面，所述晶体缺陷区域被配置为具有比用于相同应变的另一个半导体区域中的应力更低的应力; 以及通过接合部件与半导体芯片的第一主面接合的金属基板。

公开(公告)号：US08491873B2

公开(公告)日：2013-07-23

申请号：US13322752

申请日：2010-05-28

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： A61Q11/00 ,  A61K8/00 ,  A61K8/25

CPC分类号： A61Q11/00 ,  A61K8/042 ,  A61K8/25 ,  A61K8/36

摘要： Provided is a dentifrice which exhibits sufficient shape retentivity even when a polymer-based binder is not incorporated, which does not leave a taste or white residues even when the amount of powder incorporated is small, and which has satisfactory dispersibility in the oral cavity and a light feeling of use.A dentifrice containing the following components (A), (B) and (C): (A) 0.1 to 10% by mass of a thickening silica having an oil absorption of 150 to 500 mL/100 g, (B) 0.1 to 8 % by mass of heavy calcium carbonate, and (C) 40 to 70 % by mass of water at a mass ratio (B:A) of the component (B) and the component (A) of 2:1 to 0.5:99.5.

摘要翻译： 即使即使不掺入聚合物类粘合剂也不会留下味道或白色残留物，即使在粉末掺入量小的情况下也具有良好的形状保持性，并且在口腔中具有令人满意的分散性的洁齿剂 使用感轻。 含有以下成分（A），（B）和（C）的洁齿剂：（A）0.1〜10质量％的吸油量为150〜500mL / 100g的增稠二氧化硅，（B）0.1〜8 质量％的重质碳酸钙，（C）成分（B）和成分（A）的质量比（B：A）为40〜70质量％的比例为2：1〜0.5：99.5。

公开(公告)号：US08447101B2

公开(公告)日：2013-05-21

申请号：US13304471

申请日：2011-11-25

申请人： Yoshinori Murakami ,  Makio Gotoh

发明人： Yoshinori Murakami ,  Makio Gotoh

IPC分类号： G06K9/2003

CPC分类号： H04N1/58

摘要： Unevenness in density (line noise) resulting from color misregistration among RGB components in a halftone region or a line screen region is suppressed. With respect to a document that is discriminated as a printed photo document or a text/printed photo document that includes black halftones by a document type discrimination section, or to a region segmented into a black halftone region by a segmentation section, a non-uniform image suppressing operation mode is executed. In the non-uniform image suppressing operation mode, a black generation and under color removal section does not carry out a black generation and under color removal process on a pixel in which a minimum value of the image data of the plurality of color components is at least equal to or less than a predetermined threshold.

摘要翻译： 抑制了半色调区域或线条屏幕区域中的RGB分量之间的颜色重合失调导致的密度不均匀（线噪声）。 对于被区分为打印的照片文件的文档或由文档类型识别部分包括黑色半色调的文本/打印照片文档或通过分割部分分割成黑色半色调区域的区域的文档，不均匀 执行图像抑制操作模式。 在不均匀的图像抑制操作模式中，黑色产生和底色去除部分不对多个颜色分量的图像数据的最小值处于的像素执行黑色生成和颜色去除处理 最小等于或小于预定阈值。

公开(公告)号：US07521795B2

公开(公告)日：2009-04-21

申请号：US11189886

申请日：2005-07-27

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01L23/04

CPC分类号： H01L23/051 ,  H01L23/3735 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/014

摘要： A semiconductor package has: a semiconductor chip having first and second main electrodes arranged on two principal surfaces being opposite to each other; a first main wiring plate connected to the first main electrode and having a first external connection terminal; a second main wiring plate connected to the second main electrode and having a second external connection terminal; a first shell connected through an insulating film to at least a part of a second principal surface of the first main wiring plate, the second principal surface of the first main wiring plate being opposite to a first principal surface of the first main wiring plate that is connected to the first electrode; and a second shell connected through an insulating film to at least a part of a second principal surface of the second main wiring plate, the second principal surface of the second main wiring plate being opposite to a first principal surface of the second main wiring plate that is connected to the second electrode. The first principal surfaces of the first and second main wiring plates are adjacent to and parallel to each other except at the locations where the first and second main wiring plates are connected to the semiconductor chip and the locations where the first and second external connection terminals are formed.

摘要翻译： 半导体封装具有：具有彼此相对的两个主表面上布置的第一和第二主电极的半导体芯片; 连接到第一主电极并具有第一外部连接端子的第一主配线板; 连接到第二主电极并具有第二外部连接端子的第二主配线板; 第一壳体，其通过绝缘膜连接到所述第一主配线板的第二主表面的至少一部分，所述第一主配线板的第二主表面与所述第一主配线板的第一主表面相对， 连接到第一电极; 以及第二壳体，其通过绝缘膜连接到所述第二主配线板的第二主表面的至少一部分，所述第二主配线板的第二主表面与所述第二主配线板的第一主表面相对， 连接到第二电极。 除了第一和第二主配线板连接到半导体芯片的位置以及第一和第二主配线板的第一和第二外部连接端子的位置之外，第一和第二主配线板的第一主表面彼此相邻并且彼此平行 形成。

公开(公告)号：US20070166243A1

公开(公告)日：2007-07-19

申请号：US10589396

申请日：2005-03-22

申请人： Hidenori Yoshida ,  Yoshinori Murakami ,  Kazushi Oshino

发明人： Hidenori Yoshida ,  Yoshinori Murakami ,  Kazushi Oshino

IPC分类号： A61K8/73

CPC分类号： A61Q11/00 ,  A61K8/731

摘要： Provided is a dentifrice composition excellent in plaque and stain removing effect and feeling upon use. The dentifrice composition has the following components (A), (B) and (C): (A) from 0.2 to 3 weight % of powder cellulose; (B) a surfactant; and (C) from 10 to 30 weight % of an abrasive.

摘要翻译： 本发明提供了一种洁牙剂组合物，其在斑块和除斑效果以及使用感上均优异。 洁齿剂组合物具有以下组分（A），（B）和（C）：（A）0.2至3重量％的粉末纤维素; （B）表面活性剂; 和（C）10至30重量％的研磨剂。