公开(公告)号：US08520785B2

公开(公告)日：2013-08-27

申请号：US13204059

申请日：2011-08-05

Applicant: Xin He

Inventor： Xin He

IPC: H04B1/10

CPC classification number: H04B1/18

Abstract: A multimode receiver has a transconductance amplifier having an input terminal and adapted to receive a voltage RF signal and to deliver a current RF signal. The amplifier has a current mixer coupled to the transconductance amplifier and adapted to receive the current RF signal, the current mixer being adapted to combine the current RF signal with a signal generated by a local oscillator, the mixer generating an intermediate frequency signal having a frequency that equals a combination of a frequency of the current RF signal and a frequency of the local oscillator. A low-pass filter is coupled to the mixer and is adapted to generate a low-pass current signal. A transimpedance amplifier is coupled to the low-pass filter and is adapted to receive the low-pass current signal, the transimpedance amplifier being adapted to generate an intermediate frequency voltage signal proportional with the low-pass current signal. A first switch is adapted to receive a signal proportional with the intermediate frequency voltage signal at a first end, a second end being coupled to the input terminal and a second switch is coupled between the input terminal and a reference terminal. The first and second switches are mutually exclusive in an ON state in a specific mode of operation of the multimode receiver.

Abstract translation: 多模接收机具有跨导放大器，其具有输入端并适于接收电压RF信号并传送当前的RF信号。 放大器具有耦合到跨导放大器并适于接收当前RF信号的电流混频器，电流混频器适于将当前RF信号与由本地振荡器产生的信号组合，混频器产生具有频率的中频信号 这等于当前RF信号的频率与本地振荡器的频率的组合。 低通滤波器耦合到混频器并适于产生低通电流信号。 跨阻放大器耦合到低通滤波器并且适于接收低通电流信号，跨阻放大器适于产生与低通电流信号成比例的中频电压信号。 第一开关适于在第一端处接收与中频电压信号成比例的信号，第二端耦合到输入端子，第二开关耦合在输入端子和参考端子之间。 第一和第二开关在多模接收器的特定操作模式下处于ON状态下是互斥的。

公开(公告)号：US20110261914A1

公开(公告)日：2011-10-27

申请号：US13001894

申请日：2009-07-01

Applicant: Xin He ,  Jan Van Sinderen ,  Manuel Collados Asensio ,  Nenad Pavlovic

Inventor： Xin He ,  Jan Van Sinderen ,  Manuel Collados Asensio ,  Nenad Pavlovic

IPC: H04L7/00

CPC classification number: H03C5/00

Abstract: The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modulating and a computer program product. More particularly, the digital modulator comprises an output stage comprising a number of unit cell arrays, wherein the output stage comprises at least one carrier frequency signal input terminal configured to receive a carrier frequency signal. The digital modulator comprises a sampling stage connectable to the output stage, wherein the sampling stage is configured to oversample at least one data input signal. The digital modulator comprises at least one sampling clock generating device configured to generate at least one sampling clock signal depending on the number of arranged unit cell arrays and the carrier frequency signal.

Abstract translation: 本申请涉及一种数字调制器，其包括包括多个单元阵列的输出级和采样级。 本申请还涉及包括所述数字调制器，数字调制方法和计算机程序产品的通信设备。 更具体地，数字调制器包括包括多个单元阵列的输出级，其中输出级包括被配置为接收载波频率信号的至少一个载波频率信号输入端。 数字调制器包括可连接到输出级的采样级，其中采样级被配置为对至少一个数据输入信号进行过采样。 数字调制器包括至少一个采样时钟产生装置，其被配置为根据排列的单元阵列的数量和载波频率信号产生至少一个采样时钟信号。

公开(公告)号：US07774310B2

公开(公告)日：2010-08-10

申请号：US11741521

申请日：2007-04-27

Applicant: Dmitri Gavrilov ,  Xin He ,  Sanjeev Balarajan ,  Nathan Muggli

Inventor： Dmitri Gavrilov ,  Xin He ,  Sanjeev Balarajan ,  Nathan Muggli

IPC: G06F17/30

CPC classification number: G06F17/30569 ,  G06F17/30575 ,  H04L29/12132 ,  H04L61/1552 ,  H04L67/1095 ,  H04L67/28 ,  H04L67/2842 ,  H04L67/306

Abstract: A data store is distributed between a server and a client. The distributed data store includes global data. A transformation is applied to the global data to generate client-specific data based on the global data. The client-specific data is stored on the client which uses the client-specific data to perform tasks relating to the client-specific data.

Abstract translation: 数据存储分布在服务器和客户端之间。 分布式数据存储包括全局数据。 将全局数据应用于转换，以根据全局数据生成客户端特定的数据。 客户端特定数据存储在使用客户端特定数据的客户机上执行与客户端特定数据相关的任务。

公开(公告)号：US20100134154A1

公开(公告)日：2010-06-03

申请号：US12450629

申请日：2008-03-27

Applicant: Xin He

Inventor： Xin He

IPC: H03K21/00

CPC classification number: H03K23/542 ,  H03K23/544

Abstract: A method and a frequency dividing circuit (1) for dividing a frequency of an input clock signal (CLKin) by an odd number to generate an output clock signal (CLKout) with a lower frequency comprising at least two serially connected edge triggered latches clocked by said input clock signal (CLKin), wherein a last edge triggered latch of said serially connected edge triggered latches (4) inverts a triggering direction of a first edge triggered latch (4A) of said serially connected edge triggered latches (4).

Abstract translation: 一种用于将输入时钟信号（CLKin）的频率除以奇数的方法和分频电路（1），以产生具有较低频率的输出时钟信号（CLKout），该输出时钟信号包括至少两个串行连接的边缘触发锁存器，时钟频率为 所述输入时钟信号（CLKin），其中所述串行连接的边缘触发锁存器（4）的最后边缘触发锁存器使所述串行连接的边缘触发锁存器（4）的第一边缘触发锁存器（4A）的触发方向反相。

公开(公告)号：US09129992B2

公开(公告)日：2015-09-08

申请号：US13376834

申请日：2011-06-13

Applicant: Shengdong Zhang ,  Xin He ,  Longyan Wang

Inventor： Shengdong Zhang ,  Xin He ,  Longyan Wang

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: Designs and fabrication of dual-gate thin film transistors are provided. An active region and a top gate electrode of the transistor can be made of a transparent thin film material. A photoresist can be coated onto a surface of the transparent conductive thin film for forming the top gate electrode. Light is from the bottom of the substrate during exposure. After the development, a photoresist pattern aligned with the bottom gate electrode is formed on the surface of the conductive thin film. The top gate electrode aligned with the bottom gate electrode is formed by etching the conductive thin film. The bottom gate electrode can be used as a mask, which may save the cost for manufacturing the transistor and improve the accuracy of alignment between the top gate electrode and the bottom gate electrode and the performance of the dual-gate thin film transistor.

Abstract translation: 提供双栅极薄膜晶体管的设计和制造。 晶体管的有源区和顶栅电极可以由透明薄膜材料制成。 可以将光致抗蚀剂涂覆在透明导电薄膜的表面上，以形成顶栅电极。 光在曝光期间来自底物的底部。 在显影之后，在导电薄膜的表面上形成与底栅电极对准的光致抗蚀剂图案。 通过蚀刻导电薄膜来形成与底栅电极对准的顶栅电极。 底栅电极可以用作掩模，这可以节省制造晶体管的成本，并提高顶栅电极和底栅电极之间的对准精度以及双栅极薄膜晶体管的性能。

公开(公告)号：US08385475B2

公开(公告)日：2013-02-26

申请号：US12597807

申请日：2008-05-08

Applicant: Xin He ,  Johannes H. A. Brekelmans

Inventor： Xin He ,  Johannes H. A. Brekelmans

IPC: H03D1/00

CPC classification number: H03D7/14 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/1483 ,  H03D2200/0086 ,  H03K5/15093

Abstract: A circuit for producing multiple switching control signals for a harmonic rejection mixer from multiple phases of a digital local oscillator signal is presented, wherein a first waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one switching control signal by logical combining two from the multiple phases of a digital local oscillator signal, and a second waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one first switching control signal by logical combining one from the multiple phases of a digital local oscillator signal with a predetermined signal having a static logical value. To compensate for phase errors the schematic topology of the first and the second waveform combiner circuit are arranged to be fully symmetrical to each other in that in the first waveform combiner, the circuit part for providing the function of the second waveform combiner is used as a dummy circuit, and in the second waveform combiner, a circuit part for providing the function of the first waveform combiner is used as a dummy circuit. Accordingly, the sources for providing the multiple phases of the digital local oscillator signal see the same load, and hence required phase shift is guaranteed.

Abstract translation: 本发明提供了一种用于从数字本地振荡器信号的多相产生用于谐波抑制混频器的多个开关控制信号的电路，其中第一波形组合器电路被布置成从数字本地振荡器信号的多个相位产生至少一个开关控制 通过逻辑地组合来自数字本地振荡器信号的多个相位的两个信号，并且第二波形组合器电路被布置为通过逻辑地组合来自多个的多个第一切换控制信号的逻辑组合来从数字本地振荡器信号的多个相位产生至少一个第一切换控制信号 具有静态逻辑值的预定信号的数字本地振荡器信号的相位。 为了补偿相位误差，第一和第二波形组合器电路的示意性拓扑被布置为彼此完全对称，因为在第一波形组合器中，用于提供第二波形组合器的功能的电路部分被用作 虚拟电路，并且在第二波形组合器中，用作提供第一波形组合器的功能的电路部分被用作虚拟电路。 因此，用于提供数字本地振荡器信号的多相的源看到相同的负载，因此保证了所需的相移。

公开(公告)号：US20090249356A1

公开(公告)日：2009-10-01

申请号：US12060231

申请日：2008-03-31

Applicant: Xin He ,  Qi Zhang

Inventor： Xin He ,  Qi Zhang

IPC: G06F13/00

CPC classification number: G06F13/1663 ,  G06F9/526 ,  G06F9/546 ,  G06F2209/548

Abstract: Lock-free circular queues relying only on atomic aligned read/write accesses in multiprocessing systems are disclosed. In one embodiment, when comparison between a queue tail index and each queue head index indicates that there is sufficient room available in a circular queue for at least one more queue entry, a single producer thread is permitted to perform an atomic aligned write operation to the circular queue and then to update the queue tail index. Otherwise an enqueue access for the single producer thread would be denied. When a comparison between the queue tail index and a particular queue head index indicates that the circular queue contains at least one valid queue entry, a corresponding consumer thread may be permitted to perform an atomic aligned read operation from the circular queue and then to update that particular queue head index. Otherwise a dequeue access for the corresponding consumer thread would be denied.

Abstract translation: 公开了仅依赖于多处理系统中的原子对准读/写访问的无锁循环队列。 在一个实施例中，当队列尾部索引和每个队列头部索引之间的比较指示在至少一个更多队列条目的循环队列中存在足够的可用空间时，允许单个生成者线程对 循环队列，然后更新队列尾部索引。 否则，单个生产者线程的入队访问将被拒绝。 当队列尾部索引和特定队列头部索引之间的比较表示循环队列包含至少一个有效的队列条目时，可以允许相应的消费者线程从循环队列执行原子对齐的读取操作，然后更新该 特定队列头索引。 否则，相应消费者线程的出队访问将被拒绝。

公开(公告)号：US08518428B2

公开(公告)日：2013-08-27

申请号：US12747500

申请日：2009-11-17

Applicant: Qirong Shen ,  Xin He ,  Qiwei Huang ,  Xingming Yang ,  Biao Shen

Inventor： Qirong Shen ,  Xin He ,  Qiwei Huang ,  Xingming Yang ,  Biao Shen

IPC: A01N25/08

CPC classification number: A01N63/02 ,  C05F11/08 ,  C05G3/02 ,  C12N1/20 ,  C12R1/125 ,  Y02W30/43 ,  Y02W30/47

Abstract: The present invention relates to the antagonistic bacteria for controlling the Fusarium wilt of continuous cropping banana and their microbial organic fertilizer. It belongs to technology of intensive agricultural production. The present invention separates two antagonistic bacteria NJN-6 and NJN-11 and produces the microbial organic fertilizer through inoculating the two said strains into pig manure compost and rapeseed cake compost to conduct solid-state fermentation. The microbial organic fertilizer is characterized in that in the fertilizer, the content of each of the antagonistic bacteria NJN-6 and NJN-11 is above 1×108 cfu/g, total nitrogen is 4˜5% (weight percent), above 90% (weight percent) of the total nitrogen is organic nitrogen, total nitrogen-phosphorus-kalium nutrient is 6˜10% (weight percent) and organic matter is 30˜35% (weight percent). The results of experiment showed the showed that the prevention rate of the Fusarium wilt of banana reached more than 80% and the incidence rate can be controlled to less than 5% even on the seriously diseased terraces (seasonal incidence rate of 15% or more). The fertilizer can control the wilt effectively if they are applied to soil in successive years.

Abstract translation: 本发明涉及用于控制连续种植香蕉镰刀菌及其微生物有机肥的拮抗菌。 属于集约化农业生产技术。 本发明分离两种拮抗菌NJN-6和NJN-11，并通过将两种所述菌株接种到猪粪堆肥和菜籽饼堆肥中进行固态发酵来生产微生物有机肥料。 微生物有机肥的特征在于，在肥料中，每种拮抗菌NJN-6和NJN-11的含量高于1×10 8 cfu / g，总氮为4〜5％（重量百分比），高于90 总氮的百分比（重量百分比）为有机氮，总氮磷钾营养总量为6〜10％（重量百分比），有机质为30〜35％（重量百分比）。 实验结果表明，即使严重病态的梯田（季节性发病率在15％以上），香蕉枯萎病的防治率达到80％以上，发病率可控制在5％以下。 。 如果连续施用土壤，肥料可以有效地控制枯萎病。

公开(公告)号：US08362932B2

公开(公告)日：2013-01-29

申请号：US13000732

申请日：2009-06-30

Applicant: Nenad Pavlovic ,  Manel Collados Asensio ,  Xin He ,  Jan Van Sinderen

Inventor： Nenad Pavlovic ,  Manel Collados Asensio ,  Xin He ,  Jan Van Sinderen

IPC: H03M1/48

CPC classification number: H03L7/085 ,  H03L7/091

Abstract: Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit with a delay circuit input and a plurality of taps outputs. A sampling register samples data from the data inputs. The feed circuit provides for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input. A control circuit switches the feed circuit between normal operating mode and calibration mode, and controls the feed circuit successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode. The control circuit reads out resulting data from the sampling register for each selection and determines calibration data for the oscillator signal from said data.

Abstract translation: 用于校准数字转换时间的校准数据是通过在正常工作模式或校准模式之间切换时间到数字转换器的馈电电路而获得的。 具有延迟电路输入和多个抽头输出的延迟电路。 采样寄存器从数据输入端采样数据。 馈电电路提供选择振荡器信号的转变，其在延迟电路输入的转变之后控制时钟电路处的第一有源跃迁的定时。 控制电路在正常操作模式和校准模式之间切换供电电路，并且连续地控制馈电电路以选择多个不同的转变以控制校准模式中的第一主动转换的定时。 控制电路从每个选择的采样寄存器读出结果数据，并根据所述数据确定振荡器信号的校准数据。

公开(公告)号：US08198949B2

公开(公告)日：2012-06-12

申请号：US13001894

申请日：2009-07-01

Applicant: Xin He ,  Jan Van Sinderen ,  Manuel Collados Asensio ,  Nenad Pavlovic

Inventor： Xin He ,  Jan Van Sinderen ,  Manuel Collados Asensio ,  Nenad Pavlovic

IPC: H03C3/00 ,  H04L27/00 ,  H04L27/04 ,  H04L27/12 ,  H04L27/20

CPC classification number: H03C5/00

Abstract: The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modulating and a computer program product. More particularly, the digital modulator comprises an output stage comprising a number of unit cell arrays, wherein the output stage comprises at least one carrier frequency signal input terminal configured to receive a carrier frequency signal. The digital modulator comprises a sampling stage connectable to the output stage, wherein the sampling stage is configured to oversample at least one data input signal. The digital modulator comprises at least one sampling clock generating device configured to generate at least one sampling clock signal depending on the number of arranged unit cell arrays and the carrier frequency signal.

Abstract translation: 本申请涉及一种数字调制器，其包括包括多个单元阵列的输出级和采样级。 本申请还涉及包括所述数字调制器，数字调制方法和计算机程序产品的通信设备。 更具体地，数字调制器包括包括多个单元阵列的输出级，其中输出级包括被配置为接收载波频率信号的至少一个载波频率信号输入端。 数字调制器包括可连接到输出级的采样级，其中采样级被配置为对至少一个数据输入信号进行过采样。 数字调制器包括至少一个采样时钟产生装置，其被配置为根据排列的单元阵列的数量和载波频率信号产生至少一个采样时钟信号。