公开(公告)号：US20140065779A1

公开(公告)日：2014-03-06

申请号：US13376835

申请日：2011-06-13

Applicant: Shengdong Zhang ,  Ruqi Han ,  Dedong Han

Inventor： Shengdong Zhang ,  Ruqi Han ,  Dedong Han

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02488 ,  H01L21/02592 ,  H01L29/66795

Abstract: Designs and fabrication of a FinFET are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies.

Abstract translation: 提供FinFET的设计和制造。 在一个实施方式中，制造可以包括在基板上形成电介质条纹; 通过使用介电条纹作为掩模将离子注入基片，以便将基片的表面层转变成非晶层; 在覆盖所述介质条的所述基板上形成非晶半导体层，并将所述非晶层和所述非晶半导体层中的每一个重结晶为单晶层; 在介质条的两端之间的处理区域形成保护层，该区域被预先设计为源区和漏区; 在由保护层未覆盖的电介质条的两侧形成再结晶半导体间隔物，并在由保护层覆盖的区域上形成再结晶半导体块; 去除间隔物之间​​的电介质条，使得间隔物可以形成为鳍状体。

公开(公告)号：US20130309808A1

公开(公告)日：2013-11-21

申请号：US13376834

申请日：2011-06-10

Applicant: Shengdong Zhang ,  Xin He ,  Longyan Wang

Inventor： Shengdong Zhang ,  Xin He ,  Longyan Wang

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: Designs and fabrication of dual-gate thin film transistors are provided. An active region and a top gate electrode of the transistor can be made of a transparent thin film material. A photoresist can be coated onto a surface of the transparent conductive thin film for forming the top gate electrode. Light is from the bottom of the substrate during exposure. After the development, a photoresist pattern aligned with the bottom gate electrode is formed on the surface of the conductive thin film. The top gate electrode aligned with the bottom gate electrode is formed by etching the conductive thin film. The bottom gate electrode can be used as a mask, which may save the cost for manufacturing the transistor and improve the accuracy of alignment between the top gate electrode and the bottom gate electrode and the performance of the dual-gate thin film transistor.

Abstract translation: 提供双栅极薄膜晶体管的设计和制造。 晶体管的有源区和顶栅电极可以由透明薄膜材料制成。 可以将光致抗蚀剂涂覆在透明导电薄膜的表面上，以形成顶栅电极。 光在曝光期间来自底物的底部。 在显影之后，在导电薄膜的表面上形成与底栅电极对准的光致抗蚀剂图案。 通过蚀刻导电薄膜来形成与底栅电极对准的顶栅电极。 底栅电极可以用作掩模，这可以节省制造晶体管的成本，并提高顶栅电极和底栅电极之间的对准精度以及双栅极薄膜晶体管的性能。

公开(公告)号：US20130122649A1

公开(公告)日：2013-05-16

申请号：US13376833

申请日：2011-06-13

Applicant: Shengdong Zhang ,  Xin He ,  Yi Wang ,  Dedong Han ,  Ruqi Han

Inventor： Shengdong Zhang ,  Xin He ,  Yi Wang ,  Dedong Han ,  Ruqi Han

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: Disclosed is a method for manufacturing a metal oxide thin film transistor. According to the method, an active layer having a high carrier concentration is formed, and then a channel region is oxidized by plasma having oxidbillity so that the channel region has a low carrier concentration while a source region and a drain region have high carrier concentrations. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.

Abstract translation: 公开了一种金属氧化物薄膜晶体管的制造方法。 根据该方法，形成具有高载流子浓度的有源层，然后通过具有氧化性的等离子体使沟道区域氧化，使得沟道区域具有低的载流子浓度，而源区和漏区具有高的载流子浓度。 此外，晶体管的阈值电压由下述条件控制，在该条件下，晶体管的沟道区域随后在低温下具有氧化性的等离子体氧化。 因此，晶体管的特性的可控性显着提高，制造工艺简化。

公开(公告)号：US09058986B2

公开(公告)日：2015-06-16

申请号：US13376835

申请日：2011-06-13

Applicant: Shengdong Zhang ,  Ruqi Han ,  Dedong Han

Inventor： Shengdong Zhang ,  Ruqi Han ,  Dedong Han

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02488 ,  H01L21/02592 ,  H01L29/66795

Abstract: Designs and fabrication of a FinFET are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies.

Abstract translation: 提供FinFET的设计和制造。 在一个实施方式中，制造可以包括在基板上形成电介质条纹; 通过使用介电条纹作为掩模将离子注入基片，以便将基片的表面层转变成非晶层; 在覆盖所述电介质条的基板上形成非晶半导体层，并将所述非晶层和所述非晶半导体层中的每一个重结晶为单晶层; 在介质条的两端之间的处理区域形成保护层，该区域被预先设计为源区和漏区; 在由保护层未覆盖的电介质条的两侧形成再结晶半导体间隔物，并在由保护层覆盖的区域上形成再结晶半导体块; 去除间隔物之间​​的电介质条，使得间隔物可以形成为鳍状体。

公开(公告)号：US20140011329A1

公开(公告)日：2014-01-09

申请号：US13376836

申请日：2011-06-13

Applicant: Shengdong Zhang ,  Xin He ,  Yi Wang ,  Dedong Han ,  Ruqi Han

Inventor： Shengdong Zhang ,  Xin He ,  Yi Wang ,  Dedong Han ,  Ruqi Han

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: Disclosed is a method for manufacturing a self-aligned metal oxide thin film transistor. According to the present invention, a metal oxide semiconductor layer having a high carrier concentration is formed, and then a channel region which is self-aligned with a gate electrode is oxidized by a plasma having oxidbillity so that the channel region has a low carrier concentration and the source and drain regions have high carrier concentrations while the resulting transistor has a self-aligned structure. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.

Abstract translation: 公开了一种制造自对准金属氧化物薄膜晶体管的方法。 根据本发明，形成具有高载流子浓度的金属氧化物半导体层，然后与栅电极自对准的沟道区域被具有氧化性的等离子体氧化，使得沟道区域具有低载流子浓度 并且源极和漏极区域具有高的载流子浓度，而所得的晶体管具有自对准结构。 此外，晶体管的阈值电压由下述条件控制，在该条件下，晶体管的沟道区域随后在低温下具有氧化性的等离子体氧化。 因此，晶体管的特性的可控性显着提高，制造工艺简化。

公开(公告)号：US09129992B2

公开(公告)日：2015-09-08

申请号：US13376834

申请日：2011-06-13

Applicant: Shengdong Zhang ,  Xin He ,  Longyan Wang

Inventor： Shengdong Zhang ,  Xin He ,  Longyan Wang

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: Designs and fabrication of dual-gate thin film transistors are provided. An active region and a top gate electrode of the transistor can be made of a transparent thin film material. A photoresist can be coated onto a surface of the transparent conductive thin film for forming the top gate electrode. Light is from the bottom of the substrate during exposure. After the development, a photoresist pattern aligned with the bottom gate electrode is formed on the surface of the conductive thin film. The top gate electrode aligned with the bottom gate electrode is formed by etching the conductive thin film. The bottom gate electrode can be used as a mask, which may save the cost for manufacturing the transistor and improve the accuracy of alignment between the top gate electrode and the bottom gate electrode and the performance of the dual-gate thin film transistor.

Abstract translation: 提供双栅极薄膜晶体管的设计和制造。 晶体管的有源区和顶栅电极可以由透明薄膜材料制成。 可以将光致抗蚀剂涂覆在透明导电薄膜的表面上，以形成顶栅电极。 光在曝光期间来自底物的底部。 在显影之后，在导电薄膜的表面上形成与底栅电极对准的光致抗蚀剂图案。 通过蚀刻导电薄膜来形成与底栅电极对准的顶栅电极。 底栅电极可以用作掩模，这可以节省制造晶体管的成本，并提高顶栅电极和底栅电极之间的对准精度以及双栅极薄膜晶体管的性能。

公开(公告)号：US08766958B2

公开(公告)日：2014-07-01

申请号：US13386030

申请日：2011-01-26

Applicant: Shengdong Zhang ,  Congwei Liao ,  Changde He ,  Wenjun Dai

Inventor： Shengdong Zhang ,  Congwei Liao ,  Changde He ,  Wenjun Dai

IPC: G09G5/00

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving circuit unit, a gate driving circuit and a display device are disclosed. The gate driving circuit unit comprises: a first clock signal control module, an input signal control module, a third clock signal control module and a fourth clock signal control module, wherein the first clock signal control module comprises a driving unit and a clock feed-through suppressing unit. The driving unit transmits a first clock signal to an output port after being switched on. The clock feed-through suppressing unit couples the control end of the driving unit to a signal output interface under control of the first clock signal. The input signal control module provides the driving voltage for the driving unit under control of an input pulse signal. The third clock signal control module provides the shutdown voltage for the driving unit.

Abstract translation: 公开了一种栅极驱动电路单元，栅极驱动电路和显示装置。 栅极驱动电路单元包括：第一时钟信号控制模块，输入信号控制模块，第三时钟信号控制模块和第四时钟信号控制模块，其中第一时钟信号控制模块包括驱动单元和时钟馈送单元， 通过抑制单元。 驱动单元在接通之后将第一时钟信号发送到输出端口。 时钟馈通抑制单元在第一时钟信号的控制下将驱动单元的控制端耦合到信号输出接口。 输入信号控制模块在输入脉冲信号的控制下为驱动单元提供驱动电压。 第三时钟信号控制模块为驱动单元提供关断电压。

公开(公告)号：US20120188210A1

公开(公告)日：2012-07-26

申请号：US13386030

申请日：2011-01-26

Applicant: Shengdong Zhang ,  Congwei Liao ,  Changde He ,  Wenjun Dai

Inventor： Shengdong Zhang ,  Congwei Liao ,  Changde He ,  Wenjun Dai

IPC: G09G5/00 ,  H03K3/00

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving circuit unit, a gate driving circuit and a display device are disclosed. The gate driving circuit unit comprises: a first clock signal control module, an input signal control module, a third clock signal control module and a fourth clock signal control module, wherein the first clock signal control module comprises a driving unit and a clock feed-through suppressing unit. The driving unit transmits a first clock signal to an output port after being switched on. The clock feed-through suppressing unit couples the control end of the driving unit to a signal output interface under control of the first clock signal. The input signal control module provides the driving voltage for the driving unit under control of an input pulse signal. The third clock signal control module provides the shutdown voltage for the driving unit.

Abstract translation: 公开了一种栅极驱动电路单元，栅极驱动电路和显示装置。 栅极驱动电路单元包括：第一时钟信号控制模块，输入信号控制模块，第三时钟信号控制模块和第四时钟信号控制模块，其中第一时钟信号控制模块包括驱动单元和时钟馈送单元， 通过抑制单元。 驱动单元在接通之后将第一时钟信号发送到输出端口。 时钟馈通抑制单元在第一时钟信号的控制下将驱动单元的控制端耦合到信号输出接口。 输入信号控制模块在输入脉冲信号的控制下为驱动单元提供驱动电压。 第三时钟信号控制模块为驱动单元提供关断电压。

公开(公告)号：US20070181947A1

公开(公告)日：2007-08-09

申请号：US11347164

申请日：2006-02-03

Applicant: Philip Ching Ho Chan ,  Man Sun Chan ,  Xusheng Wu ,  Shengdong Zhang

Inventor： Philip Ching Ho Chan ,  Man Sun Chan ,  Xusheng Wu ,  Shengdong Zhang

IPC: H01L27/12

CPC classification number: H01L29/785 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A multi-layer fin may be formed on the insulating layer and may include two semiconducting layers isolated by an insulating layer in vertical direction. A first MOS type device comprising a first source region, a first channel region and a first drain region is arranged on the first semiconducting layer in the multi-layer fin. A second MOS type device comprising a second source region, a second channel region and a second drain region is arranged on the second semiconducting layer in the multi-layer fin. A gate electrode is provided so as to be vertically adjacent to the first and second channel regions.

Abstract translation: 半导体器件可以包括衬底和形成在衬底上的绝缘层。 可以在绝缘层上形成多层鳍，并且可以包括在垂直方向上被绝缘层隔离的两个半导体层。 包括第一源极区域，第一沟道区域和第一漏极区域的第一MOS型器件被布置在多层鳍片的第一半导体层上。 包括第二源极区，第二沟道区和第二漏极区的第二MOS型器件布置在多层鳍中的第二半导体层上。 栅电极设置成与第一和第二沟道区垂直相邻。

公开(公告)号：US08956926B2

公开(公告)日：2015-02-17

申请号：US13376836

申请日：2011-06-13

Applicant: Shengdong Zhang ,  Xin He ,  Yi Wang ,  Dedong Han ,  Jeng Han

Inventor： Shengdong Zhang ,  Xin He ,  Yi Wang ,  Dedong Han ,  Ruqi Han

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: Disclosed is a method for manufacturing a self-aligned metal oxide thin film transistor. According to the present invention, a metal oxide semiconductor layer having a high carrier concentration is formed, and then a channel region which is self-aligned with a gate electrode is oxidized by a plasma having oxidbillity so that the channel region has a low carrier concentration and the source and drain regions have high carrier concentrations while the resulting transistor has a self-aligned structure. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.

Abstract translation: 公开了一种制造自对准金属氧化物薄膜晶体管的方法。 根据本发明，形成具有高载流子浓度的金属氧化物半导体层，然后与栅电极自对准的沟道区域被具有氧化性的等离子体氧化，使得沟道区域具有低载流子浓度 并且源极和漏极区域具有高的载流子浓度，而所得的晶体管具有自对准结构。 此外，晶体管的阈值电压由下述条件控制，在该条件下，晶体管的沟道区域随后在低温下具有氧化性的等离子体氧化。 因此，晶体管的特性的可控性显着提高，制造工艺简化。