A gate driving circuit unit, a gate driving circuit and a display device are disclosed. The gate driving circuit unit comprises: a first clock signal control module, an input signal control module, a third clock signal control module and a fourth clock signal control module, wherein the first clock signal control module comprises a driving unit and a clock feed-through suppressing unit. The driving unit transmits a first clock signal to an output port after being switched on. The clock feed-through suppressing unit couples the control end of the driving unit to a signal output interface under control of the first clock signal. The input signal control module provides the driving voltage for the driving unit under control of an input pulse signal. The third clock signal control module provides the shutdown voltage for the driving unit.