公开(公告)号：US11282824B2

公开(公告)日：2022-03-22

申请号：US16392170

申请日：2019-04-23

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

公开(公告)号：US11276098B2

公开(公告)日：2022-03-15

申请号：US15793332

申请日：2017-10-25

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  Wei Yee Jocelyn Teo ,  Craig E. Taylor

IPC: G06Q30/06 ,  G06F21/30 ,  G06K7/10 ,  G06F16/903 ,  G06F30/00

Abstract: Embodiments described herein include techniques for providing information regarding a hardware part using a scannable code so that a customer can make an informed decision when placing the hardware part in a larger computing system. A customer may purchase hardware parts that are categorized into a certain bin which has guaranteed range of power consumption or performance. The customer may over design the computing system to accommodate the worst parameter in the range (e.g., the minimum performance or the maximum power consumption) to ensure the timing or power specifications are not violated. Instead, the embodiments herein provide a scannable code on the hardware part which the customer can use to access a database which stores more granular information about the part. The customer can use the performance parameters to make better informed decisions to determine where to place the part in the computing system.

公开(公告)号：US10956638B1

公开(公告)日：2021-03-23

申请号：US16514324

申请日：2019-07-17

Applicant: XILINX, INC.

Inventor： Bart Reynolds ,  Xiaojian Yang ,  Matthew H. Klein

IPC: G06F30/331 ,  G06F30/392 ,  G06F30/398

Abstract: Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.

公开(公告)号：US10665515B1

公开(公告)日：2020-05-26

申请号：US16026981

申请日：2018-07-03

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  Gregory Meredith ,  Joshua Tan

IPC: H01L23/58 ,  H01L21/66 ,  H01L27/118 ,  G01R31/317 ,  G06F30/392

Abstract: Embodiments herein describe binning and placement techniques for assembling a multi-die device to improve yield when a customer requests a high performance feature from the device. For example, the multi-die device may include multiple dies that are interconnected to form a single device or package. In one embodiment, the multiple dies are the same semiconductor die (e.g., have the same circuit layout) which are disposed on a common interposer or stacked on each other. The multi-die device can then be attached to a printed circuit board (PCB). Although the dies in the multi-die device may each include the same feature (e.g., a PCIe interface, SerDes interface, transmitter, memory interface, etc.), the multi-die device is assembled so that not all of the dies have a feature that satisfies the high performance requested by the customer. That is, at least one of the die includes a lower performance feature.

公开(公告)号：US10204841B1

公开(公告)日：2019-02-12

申请号：US15369545

申请日：2016-12-05

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  Raghunandan Chaware

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L21/78

Abstract: A method for fabricating integrated circuit (IC) dies and wafers having such dies, are disclosed herein that leverage temporary connection traces during wafer level testing of the functionality of the IC die. In one example, a wafer includes a plurality of IC dies. At least a first IC die of the plurality of IC dies includes a plurality of micro-bumps and a first temporary connection trace formed on an exterior surface of the die body. The plurality of micro-bumps includes at least a first micro-bump and a second micro-bump. The first temporary connection trace electrically couples the first micro-bump and the second micro-bump.

公开(公告)号：US09000490B2

公开(公告)日：2015-04-07

申请号：US13866893

申请日：2013-04-19

Applicant: Xilinx, Inc.

Inventor： Thao H. T. Vo ,  Andy H. Gan ,  Xiao-Yu Li ,  Matthew H. Klein

IPC: G06F1/32 ,  H01L25/065 ,  G06F17/50

CPC classification number: H01L25/0652 ,  G06F1/3203 ,  G06F1/324 ,  G06F17/5045 ,  G06F17/5054 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.

Abstract translation: 半导体封装包括插入件和多个集成电路（IC）芯片，其经由插入器设置并耦合。 第一个IC芯片的时钟速度等级大于另一个IC芯片的时钟速度等级。 多个可编程电压调谐器分别耦合到多个IC芯片。 第一电压调谐器耦合到第一IC芯片，并且第一电压调谐器被编程以降低输入到第一电压调谐器的电压的电压电平，并将降低的电压输出到第一IC芯片。

公开(公告)号：US08966432B1

公开(公告)日：2015-02-24

申请号：US14019897

申请日：2013-09-06

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/505 ,  G06F2217/62 ,  G06F2217/84

Abstract: Reducing jitter in a circuit design includes selecting a plurality of circuit elements of a circuit design clocked using a first clock signal and assigning, using a processor, the plurality of circuit elements to different ones of a plurality of groups according to a balancing criterion. The circuit elements assigned to a first group of the plurality of groups are clocked using the first clock signal. The circuit elements assigned to a second group of the plurality of groups are clocked using a second clock signal different from the first clock signal.

Abstract translation: 降低电路设计中的抖动包括选择使用第一时钟信号计时的电路设计的多个电路元件，并且根据平衡标准将多个电路元件分配给多个组中的不同组。 分配给多个组中的第一组的电路元件使用第一时钟信号来计时。 使用不同于第一时钟信号的第二时钟信号对分配给多个组中的第二组的电路元件进行时钟控制。