公开(公告)号：US10707138B1

公开(公告)日：2020-07-07

申请号：US15473395

申请日：2017-03-29

Applicant: Xilinx, Inc.

Inventor： Shiying Xiong ,  Thao H. T. Vo ,  Felino E. Pagaduan ,  Qi Xiang ,  Xiao-Yu Li ,  Glenn O'Rourke

IPC: H01L21/67 ,  H01L21/66 ,  H01L25/00

Abstract: An integrated circuit (IC) chip package assembly apparatus and techniques for assembling IC chip packages are described. For example, a techniques for fabricating an IC package include (A) determining a first package assembly yield (PAY) across a first die pool comprising a first plurality of dies having a performance criteria within a first predefined range; (B) determining a second PAY across a second die pool comprising a second plurality of dies having a performance criteria within a second predefined range of performance criteria that is different than the first predefined range of performance criteria, the second plurality of dies comprising a portion of the first plurality of dies; and (C) generating a final assembly sequence in response to analyzing the first and second PAYs, the final assembly sequence comprising rules for combining dies in accordance with obtaining a higher of the first PAY and the second PAY.

公开(公告)号：US09000490B2

公开(公告)日：2015-04-07

申请号：US13866893

申请日：2013-04-19

Applicant: Xilinx, Inc.

Inventor： Thao H. T. Vo ,  Andy H. Gan ,  Xiao-Yu Li ,  Matthew H. Klein

IPC: G06F1/32 ,  H01L25/065 ,  G06F17/50

CPC classification number: H01L25/0652 ,  G06F1/3203 ,  G06F1/324 ,  G06F17/5045 ,  G06F17/5054 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.

Abstract translation: 半导体封装包括插入件和多个集成电路（IC）芯片，其经由插入器设置并耦合。 第一个IC芯片的时钟速度等级大于另一个IC芯片的时钟速度等级。 多个可编程电压调谐器分别耦合到多个IC芯片。 第一电压调谐器耦合到第一IC芯片，并且第一电压调谐器被编程以降低输入到第一电压调谐器的电压的电压电平，并将降低的电压输出到第一IC芯片。