公开(公告)号：US10256968B1

公开(公告)日：2019-04-09

申请号：US15660141

申请日：2017-07-26

Applicant: Xilinx, Inc.

Inventor： Zhaoyin D. Wu ,  Yu Xu ,  Winson Lin ,  Yohan Frans ,  Geoffrey Zhang

IPC: H04L7/00 ,  H03L7/081 ,  H04L7/033

Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

公开(公告)号：US10038545B1

公开(公告)日：2018-07-31

申请号：US15660397

申请日：2017-07-26

Applicant: Xilinx, Inc.

Inventor： Zhaoyin D. Wu ,  Winson Lin ,  Yu Xu ,  Geoffrey Zhang

IPC: H03L7/08 ,  H03L7/00 ,  H04L7/00 ,  H03L7/081 ,  H04L7/033 ,  H04L12/26

CPC classification number: H04L7/0025 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H04L7/0004 ,  H04L7/0012 ,  H04L7/033 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/0338 ,  H04L43/028 ,  H04L43/16

Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.

公开(公告)号：US09595990B1

公开(公告)日：2017-03-14

申请号：US15158420

申请日：2016-05-18

Applicant: Xilinx, Inc.

Inventor： Hongtao Zhang ,  Geoffrey Zhang

IPC: H04L27/06 ,  H04B1/12 ,  H03G3/20

CPC classification number: H04L25/03878 ,  H03G3/3078

Abstract: A circuit for enabling an adaptation of an automatic gain control circuit comprises an automatic gain control (ACG) circuit configured to receive an input signal and to generate a boosted input signal. An average peak signal magnitude adaptation circuit is configured to receive an output of a decision circuit and to generate an average peak signal magnitude. An average peak signal target calculation circuit is configured to receive the average peak signal magnitude and detected peak signal magnitudes, wherein the average peak signal magnitude adaptation circuit generates a target peak signal magnitude. An AGC adaptation circuit is configured to receive an average peak signal magnitude and the target peak signal magnitude, wherein the AGC adaptation circuit provides an AGC control signal to the AGC circuit to maximize the effective signal magnitude within an acceptable linearity range.

Abstract translation: 用于实现自动增益控制电路的自适应的电路包括被配置为接收输入信号并产生升压的输入信号的自动增益控制（ACG）电路。 平均峰值信号幅度自适应电路被配置为接收判定电路的输出并产生平均峰值信号幅度。 平均峰值信号目标计算电路被配置为接收平均峰值信号幅度和检测到的峰值信号幅度，其中平均峰值信号幅度适配电路产生目标峰值信号幅度。 AGC适配电路被配置为接收平均峰值信号幅度和目标峰值信号幅度，其中AGC适配电路向AGC电路提供AGC控制信号，以使可接受的线性范围内的有效信号幅度最大化。

公开(公告)号：US09455848B1

公开(公告)日：2016-09-27

申请号：US14829318

申请日：2015-08-18

Applicant: Xilinx, Inc.

Inventor： Hongtao Zhang ,  Geoffrey Zhang ,  Kun-Yung Chang

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03057 ,  H04L7/0025 ,  H04L7/0062 ,  H04L7/0087 ,  H04L2025/03611

Abstract: In an example, an apparatus for clock data recovery (CDR) in a receiver includes a decision feedback equalizer (DFE) having a data slicer providing data samples, an error slicer providing error samples, and an offset error slicer providing offset error samples, the offset error slicer operable to set its threshold based on an offset first post-cursor coefficient. The apparatus further includes a CDR circuit operable to control a sampling clock for the data slicer, the error slicer, and the offset error slicer based on the data samples and the offset error samples.

Abstract translation: 在一个示例中，接收机中用于时钟数据恢复（CDR）的装置包括具有提供数据样本的数据限幅器的判定反馈均衡器（DFE），提供误差采样的误差限幅器和提供偏移误差采样的偏移误差限幅器， 偏移误差限幅器，其可操作以基于偏移的第一后置光标系数来设置其阈值。 该装置还包括CDR电路，其可操作以基于数据样本和偏移误差样本来控制数据限幅器，误差限幅器和偏移误差限幅器的采样时钟。

公开(公告)号：US09438409B1

公开(公告)日：2016-09-06

申请号：US14789738

申请日：2015-07-01

Applicant: Xilinx, Inc.

Inventor： Yu Liao ,  Geoffrey Zhang

IPC: H03H7/30 ,  H04L7/00 ,  H04L7/04 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/0062 ,  H04L7/0087

Abstract: In an example, an apparatus for clock data recovery (CDR) includes a data slicer operable to generate data samples derived from a transmitted signal, and an error slicer operable to generate error samples derived from a transmitted signal. The apparatus further includes a CDR circuit operable to generate sampling clock phase for the data slicer and the error slicer from output of the data samples and the error samples. The apparatus further includes a decision adapt circuit operable to set a decision threshold of the error slicer, wherein for each main-cursor data sample of the data samples the decision adapt circuit is operable to adjust the decision threshold based on a function of at least one pre-cursor data sample, at least one post-cursor data sample, or a combination of at least one pre-cursor data sample and at least one post-cursor data sample.

Abstract translation: 在一个示例中，用于时钟数据恢复（CDR）的装置包括可操作以产生从发送信号导出的数据样本的数据限幅器，以及用于产生从发送信号导出的误差样本的差错限幅器。 该装置还包括CDR电路，可操作以从数据样本和误差样本的输出产生数据限幅器和误差限幅器的采样时钟相位。 所述装置还包括判定适配电路，其可操作以设置所述误差限幅器的判定阈值，其中，对于所述数据样本的每个主光标数据采样，所述判定适配电路可操作以基于至少一个 前标数据样本，至少一个后标记数据样本或至少一个前置标准数据样本和至少一个后视标数据样本的组合。

公开(公告)号：US09178552B1

公开(公告)日：2015-11-03

申请号：US14547394

申请日：2014-11-19

Applicant: Xilinx, Inc.

Inventor： Patrick Satarzadeh ,  Hongtao Zhang ,  Geoffrey Zhang ,  Zhaoyin D. Wu

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04B1/16 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04B1/16 ,  H04L25/03057 ,  H04L2025/03547

Abstract: In a method for channel adaptation, an analog input signal is received with a bimodal receiver via a communications channel. The analog input signal is converted to a digital input signal with an analog-to-digital converter of a digital receiver of the bimodal receiver. Channel coefficients are detected for the digital input signal associated with the communications channel. The channel coefficients indicate a number of post-cursor taps of the bimodal receiver to be used to provide an equalized digital output signal from the digital input signal. It is determined whether the number of post-cursor taps or a value associated therewith is equal to or less than a threshold number. A switch from the receiving of the analog input signal by the digital receiver to an analog receiver of the bimodal receiver is made to provide the equalized digital output signal for the analog input signal.

Abstract translation: 在一种用于信道适配的方法中，通过通信信道用双模接收机接收模拟输入信号。 模拟输入信号通过双模接收器的数字接收器的模数转换器转换为数字输入信号。 检测与通信信道相关联的数字输入信号的信道系数。 信道系数指示用于从数字输入信号提供均衡的数字输出信号的双模接收机的多个后置光标抽头。 确定后视标抽头的数量或与其相关联的值是否等于或小于阈值数。 使得从数字接收机将模拟输入信号接收到双模接收机的模拟接收机的切换是为模拟输入信号提供均衡的数字输出信号。