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公开(公告)号:US12068330B2
公开(公告)日:2024-08-20
申请号:US16966116
申请日:2020-01-17
Inventor: Yuan Yan , Yong Xu , Fei Ai , Dewei Song
CPC classification number: H01L27/124 , G06F3/041 , G06F3/0412 , G06F3/04164 , G06F3/0443 , H01L27/1288 , G06F2203/04103
Abstract: A touch array substrate and a manufacturing method thereof, wherein in the touch array substrate, an active layer, an insulating layer, a pixel electrode layer, a metal layer, a planarization layer, and a common electrode layer are sequentially disposed on the buffer layer. The active layer includes a first region corresponding to a source electrode and a second region corresponding to a drain electrode. The pixel electrode layer includes a plurality of base layers. The metal layer is correspondingly disposed on the base layers. The metal layer includes a touch signal line, a data line, and a gate electrode. The common electrode layer includes a touch electrode, the source electrode, and the drain electrode.
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公开(公告)号:US20240222446A1
公开(公告)日:2024-07-04
申请号:US17996787
申请日:2022-08-30
Inventor: Fei Ai , Dewei Song
IPC: H01L29/417 , H01L29/08 , H01L29/49 , H01L29/66 , H01L29/786
CPC classification number: H01L29/41733 , H01L29/0847 , H01L29/4908 , H01L29/66757 , H01L29/66969 , H01L29/78675 , H01L29/7869
Abstract: The present application provides a thin film transistor and an electronic device. The thin film transistor includes: a crystalline active pattern, wherein the crystalline active pattern includes a channel and two contact portions, and the two contact portions are connected to opposite two sides of the channel in a direction intersecting a thickness direction of the crystalline active pattern; a groove located on at least one of the two contact portions and extending in the thickness direction of the crystalline active pattern; a source electrode and a drain electrode connected to the two contact portions, respectively; and an insulating layer being in contact with the channel.
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公开(公告)号:US20240027859A1
公开(公告)日:2024-01-25
申请号:US17607852
申请日:2021-09-08
Inventor: Zhilin Wu , Tao Ma , Dewei Song , Fei Ai
IPC: G02F1/1362 , G02F1/1343 , G02F1/1333 , G02F1/1368
CPC classification number: G02F1/136295 , G02F1/136209 , G02F1/1343 , G02F1/136227 , G02F1/13338 , G02F1/1368
Abstract: The present application discloses a display panel and an electrical terminal. The display panel includes: an underlay; an array driver layer located on the underlay and including a gate electrode layer and a source and drain electrode layer; a signal line including an adaptor portion located in the non-display region, wherein the adaptor portion includes a first wire section disposed in a same layer with the gate electrode layer, a second wire section disposed in a same layer with the source and drain electrode layer, and a bridge portion electrically connected to the first wire section and the second wire section; wherein the first wire section, the second wire section, and the bridge portion are disposed in different layers.
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公开(公告)号:US10964790B1
公开(公告)日:2021-03-30
申请号:US16097838
申请日:2018-09-14
Inventor: Yuan Yan , Lisheng Li , Dewei Song
IPC: H01L29/417 , H01L29/66 , H01L29/786 , H01L27/12 , H01L29/45 , H01L21/311
Abstract: The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.
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