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公开(公告)号：US12125424B2
公开(公告)日：2024-10-22
申请号：US17605546
申请日：2021-08-31
Inventor： Mingyue Li , Chao Tian , Yanqing Guan , Fei Ai , Guanghui Liu
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/0286
Abstract: The present application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded gate driving modules. A first driving signal can be output through a first output node, and at the same time, a second driving signal with a same phase as the first driving signal can be output through a second output node, and a gate driving sub-module and an in-phase output sub-module share the first output node and a pull-down node, which simplifies a circuit topology of the gate driving circuit.
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公开(公告)号：US12067916B2
公开(公告)日：2024-08-20
申请号：US17434726
申请日：2021-06-01
Inventor： Yongxiang Zhou , Chao Tian
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2300/0426 , G09G2310/0286 , G09G2320/0214
Abstract: A driving circuit and a display panel are provided. The driving circuit includes a plurality of driving units which are cascaded. An Nth stage driving unit includes: a pull-up control module; a first bootstrap module; a pull-up module; a pull-down control module; and a first pull-down module. The driving circuit can be normally operated by input signal lines including a first clock signal line, a second clock signal line, a first power signal line, a second power signal line, and an initial signal line, so that types and a number of the input signal lines can be effectively reduced.
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公开(公告)号：US12014666B2
公开(公告)日：2024-06-18
申请号：US17976803
申请日：2022-10-30
Inventor： Haiming Cao , Chao Tian , Fei Ai , Guanghui Liu
IPC: G09G3/32 , G09G3/20 , G09G3/3233
CPC classification number: G09G3/2014 , G09G3/32 , G09G2300/0842 , G09G2310/0264 , G09G2310/08 , G09G2320/0242 , G09G2320/0633
Abstract: A pixel driving circuit and a display panel are provided. The pixel driving circuit includes a data writing module, a data conversion module, and a current driving module. The data writing module is electrically connected to a first node and configured to transmit a data signal to the first node. The data conversion module is electrically connected to the first node, a second node, and a modulation signal source, and configured to generate a current driving control signal, and to output the current driving control signal to the second node. The current driving module is electrically connected to the second node, a light-emitting control wire, and a light-emitting device, and configured to control the light-emitting device to emit light. An effective pulse of the current driving control signal has different pulse widths in different gray-scale states.
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公开(公告)号：US20240021122A1
公开(公告)日：2024-01-18
申请号：US17605546
申请日：2021-08-31
Inventor： Mingyue Li , Chao Tian , Yanqing Guan , Fei Ai , Guanghui Liu
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/0286
Abstract: The present application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded gate driving modules. A first driving signal can be output through a first output node, and at the same time, a second driving signal with a same phase as the first driving signal can be output through a second output node, and a gate driving sub-module and an in-phase output sub-module share the first output node and a pull-down node, which simplifies a circuit topology of the gate driving circuit.
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公开(公告)号：US11862064B2
公开(公告)日：2024-01-02
申请号：US16970636
申请日：2020-06-15
Inventor： Chao Tian
IPC: G09G3/20
CPC classification number: G09G3/2096 , G09G2300/0408 , G09G2300/0426 , G09G2300/0876 , G09G2310/08
Abstract: An array substrate and a display panel are disclosed; at least one GOA circuit is provided in a pixel area of a same row, all GOA circuits of the same row are connected to a same scan line, and each GOA circuit of the same row is connected to a driving IC through a corresponding driving signal line. By setting the GOA circuit in a display area, a near bezel-free display panel design can be realized. Meanwhile, the GOA circuit is modularly designed to form an independent layout model, which improves design efficiency.
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Patent Agency Ranking
公开(公告)号：US20230402019A1
公开(公告)日：2023-12-14
申请号：US17419876
申请日：2021-05-31
Inventor： Yanqing Guan , Chao Tian , Haiming Cao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0876
Abstract: A display panel and a gate driving circuit are provided. The gate driving circuit utilizes the pull-down control module to periodically pull up and pull down the voltage level of the second node. The voltage level of the second node is periodically a high voltage level. This effectively reduces the time duration when the second node corresponds to the high voltage level. After the TFTs electrically connected to the second node are forward biased, the TFTs could have sufficient recovery time. This solution effectively improves the bias condition of the TFTs in the pull-down control module and thus makes the circuit more stable and raises the reliability of the circuit.
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公开(公告)号：US11837172B2
公开(公告)日：2023-12-05
申请号：US17622633
申请日：2021-12-15
Inventor： Chao Tian , Yanqing Guan , Guanghui Liu , Fei Ai
IPC: G09G3/3266 , G06F3/041 , G09G3/36
CPC classification number: G09G3/3266 , G06F3/0412 , G06F3/0418 , G06F3/04166 , G09G3/3674 , G09G2310/08 , G09G2354/00
Abstract: A gate driving circuit and a display device are provided. The gate driving circuit includes electrically connected multi-stage driving units. The driving unit of each stage includes an input module, an output module electrically connected with the input module, a pull-down module electrically connected with the output module, and a pull-down control module electrically connected with the pull-down module. The output module is electrically connected to a stage transmission signal output terminal, and the pull-down module is electrically connected to a first control signal terminal.
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公开(公告)号：US11816278B1
公开(公告)日：2023-11-14
申请号：US18050794
申请日：2022-10-28
Inventor： Shengyang Chen , Chao Tian , Fei Ai
CPC classification number: G06F3/0412 , G06F3/0446
Abstract: A display panel and an electronic device are provided. The display panel includes a substrate, first touch coils, pad groups, light-emitting units, and connection lines. The first touch coils are disposed on the substrate. The pad groups are disposed on the substrate. The pad groups are disposed on a side of the first touch coils facing away the substrate. The light-emitting units are disposed on the corresponding pad groups. The connection lines are disposed insulated from the first touch coils. The connection lines are connected to two pad groups. The connection lines and the first touch coils are disposed in different layers. The connection lines intersect with the first touch coils. Intersection positions of the connection lines and the first touch coils form overlapping regions. Concave portions are defined at a surface of the connection lines close to the first touch coils.
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公开(公告)号：US11715436B2
公开(公告)日：2023-08-01
申请号：US17281600
申请日：2021-03-15
Inventor： Chao Tian , Haiming Cao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0819
Abstract: In a GOA circuit provided by the present disclosure, a unidirectional feedback circuit is adopted between a first node and a second node of the GOA circuit of the present disclosure, which can reduce complexity of circuit design, make it easier to achieve linear design and in-plane integration, prevent point competition of the first node and the second node, and improve stability of the circuit.
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公开(公告)号：US11139316B2
公开(公告)日：2021-10-05
申请号：US16097917
申请日：2018-08-01
Inventor： Chao Tian , Juncheng Xiao
IPC: H01L27/12
Abstract: The present disclosure provides an LTPS array substrate and a method for manufacturing the same. The method includes forming a polysilicon pattern by a first mask process; performing a doping treatment on the polysilicon pattern and forming a gate electrode by a second mask process; forming a source electrode through-hole and a drain electrode through-hole and a pixel electrode by a third mask process; forming a source electrode and a drain electrode and a touch control signal line by a fourth mask process; forming a touch control electrode through-hole by a fifth mask process; and forming a touch control electrode by a sixth mask process.
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