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21.发明授权Materials and methods for sublithographic patterning of gate structures in integrated circuit devices 失效用于集成电路器件中栅极结构的亚光刻图案的材料和方法公开(公告)号：US06884735B1
公开(公告)日：2005-04-26
申请号：US10224876
申请日：2002-08-21
IPC分类号： G03F7/26 , G03F7/38 , H01L21/027 , H01L21/28 , H01L21/302 , G03C5/00
CPC分类号： G03F7/26 , G03F7/38 , H01L21/0271 , H01L21/0274 , H01L21/28123
摘要： An integrated circuit fabrication process including exposing a photoresist layer and providing a hydrophilic layer above the photoresist layer. The photoresist layer is exposed to a pattern of electromagnetic energy. The polymers in the hydrophilic layer can diffuse into the photoresist layer after provision of the hydrophilic layer. The diffusion can lead to plasticization of the photoresist layer polymers in exposed regions relative to unexposed regions. The process can be utilized to form a large variety of integrated circuit structures including gate structures and other features with wide process latitude and smooth feature side walls.
摘要翻译： 一种集成电路制造工艺，包括曝光光致抗蚀剂层并在光致抗蚀剂层之上提供亲水层。 光致抗蚀剂层暴露于电磁能的图案。 在提供亲水层之后，亲水层中的聚合物可以扩散到光致抗蚀剂层中。 扩散可导致相对于未曝光区域的曝光区域中的光致抗蚀剂层聚合物的增塑。 该方法可用于形成各种各样的集成电路结构，包括门结构和具有宽工艺纬度和光滑特征侧壁的其它特征。
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公开(公告)号：US06774365B2
公开(公告)日：2004-08-10
申请号：US09820143
申请日：2001-03-28
IPC分类号： G01N2300
CPC分类号： H01L21/28123
摘要： A process for improving the accuracy of critical dimension measurements of features patterned on a photoresist layer using a scanning electron microscope (SEM) is disclosed herein. The process includes providing an electron beam to the photoresist layer and transforming the surface of the photoresist layer before the SEM inspection. The surface of the photoresist layer is transformed to trap the outgassing volatile species and dissipates built up charge in the photoresist layer, resulting in SEM images without poor image contrast.
摘要翻译： 本文公开了使用扫描电子显微镜（SEM）提高在光致抗蚀剂层上图案化的特征的临界尺寸测量的精度的方法。 该方法包括在SEM检查之前向光致抗蚀剂层提供电子束并转换光致抗蚀剂层的表面。 转变光致抗蚀剂层的表面以捕获除气挥发性物质并在光致抗蚀剂层中消散积聚电荷，导致SEM图像，而图像对比度差。
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23.发明授权Method(s) facilitating formation of memory cell(s) and patterned conductive 失效促进形成记忆体和图案化的导电聚合物膜的方法公开(公告)号：US06753247B1
公开(公告)日：2004-06-22
申请号：US10285183
申请日：2002-10-31
申请人： Uzodinma Okoroanyanwu , Suzette K. Pangrle , Matthew S. Buynoski , Nicholas H. Tripsas , Mark S. Chang , Ramkumar Subramanian , Angela T. Hui
发明人： Uzodinma Okoroanyanwu , Suzette K. Pangrle , Matthew S. Buynoski , Nicholas H. Tripsas , Mark S. Chang , Ramkumar Subramanian , Angela T. Hui
IPC分类号： H01L214763
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L27/285
摘要： A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is applied over the stack to at least fill in the first via. A second via is then etched into the dielectric material so as to expose and make the electrode layer available as a top electrode. A wordline is then formed over the dielectric material such that the top electrode is connected to the wordline by way of the second via. A memory device formed in accordance with the disclosed methodology includes a top electrode formed over an organic polymer layer, a conductive layer under the organic polymer layer, a via defined by a dielectric material and located above the top electrode, and a wordline formed over the dielectric material such that the top electrode is connected to the wordline by way of the via.
摘要翻译： 公开了一种用于形成存储单元的方法，其中在导电层上形成有机聚合物层，并且在有机聚合物层上形成电极层。 将第一通孔蚀刻到电极和有机聚合物层中，并且将电介质材料施加到堆叠上以至少填充在第一通孔中。 然后将第二通道蚀刻到电介质材料中，以暴露并使电极层可用作顶部电极。 然后在电介质材料上形成字线，使得顶部电极通过第二通孔连接到字线。 根据所公开的方法形成的存储器件包括形成在有机聚合物层上的顶部电极，有机聚合物层下面的导电层，由电介质材料限定并位于顶部电极之上的通孔，以及形成在上部电极上的字线 电介质材料，使得顶部电极通过通孔连接到字线。
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24.发明授权Process for reducing critical dimensions of contact holes, vias, and trench structures in integrated circuits 失效用于减小集成电路中接触孔，通孔和沟槽结构的关键尺寸的工艺公开(公告)号：US06518175B1
公开(公告)日：2003-02-11
申请号：US09771842
申请日：2001-01-29
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/0273 , H01L21/3088 , H01L21/32139 , H01L21/76816 , Y10S438/948 , Y10S438/961
摘要： An integrated circuit fabrication process to pattern reduced feature size is disclosed herein. The process includes reducing the width of a patterned area of a patterned photoresist layer provided over a substrate before patterning the substrate. The patterned area is representative of a feature to be formed in the substrate. The width of the feature is reduced by an electron beam mediated heating and flowing of select areas of the patterned photoresist layer.
摘要翻译： 本文公开了一种用于对特征尺寸缩小的集成电路制造工艺。 该方法包括在图案化衬底之前减小设置在衬底上的图案化光致抗蚀剂层的图案化区域的宽度。 图案化区域代表要在基底中形成的特征。 通过电子束介导的加热和图案化光致抗蚀剂层的选择区域的流动来减小特征的宽度。
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25.发明授权Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques 有权具有低k介电材料的互连结构和使用单镶嵌和双镶嵌技术制作相同的方法
公开(公告)号：US06127089A
公开(公告)日：2000-10-03
申请号：US143105
申请日：1998-08-28
IPC分类号： G03F7/075 , H01L21/311 , H01L21/768 , G03C1/76
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76802 , H01L21/76807 , G03F7/075
摘要： A damascene structure and method of making the same in a low k dielectric material employs an imageable layer in which the damascene pattern is provided. The imageable layer is a convertible layer that upon exposure to the plasma etch that etches the low k dielectric material, converts the silicon-rich imageble layer into a mask layer containing silicon dioxide, for example. The low k dielectric material is protected from further etching by the mask thus created.
摘要翻译： 一种镶嵌结构及其在低k电介质材料中的制造方法采用其中提供镶嵌图案的可成像层。 可成像层是可转换层，其在暴露于蚀刻低k介电材料的等离子体蚀刻时，例如将富含硅的图像层转换成含有二氧化硅的掩模层。 通过由此产生的掩模来保护低k电介质材料免于进一步蚀刻。
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26.发明授权公开(公告)号：US07465956B1
公开(公告)日：2008-12-16
申请号：US11251999
申请日：2005-10-17
IPC分类号： H01L51/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0078
摘要： The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.
摘要翻译： 本发明提供一种多层有机存储器件，其可以作为其中构造有多个堆叠和/或并行存储器结构的非易失性存储器件来操作。 可以在两个或多个电极之间形成多单元和多层有机存储器组件，所述两个或更多个电极在形成各个单元的电极之间具有选择性导电介质，同时利用分隔组件使得能够堆叠额外的存储器单元， 以前形成的细胞。 可以通过添加额外的层 - 通过附加分隔部件分开的相应层来形成存储器堆叠，其中可以并行形成多个堆叠以提供高密度存储器件。
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27.发明授权公开(公告)号：US07368225B1
公开(公告)日：2008-05-06
申请号：US10925123
申请日：2004-08-24
申请人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eil Kim
发明人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eil Kim
IPC分类号： G03F7/00
CPC分类号： G03F1/00 , H01L21/76816
摘要： There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.
摘要翻译： 提供了在第一层中制作多个特征的方法。 在第一层上形成光致抗蚀剂层。 光致抗蚀剂层中的密集区域在第一组照射条件下通过第一掩模曝光。 在与第一组照明条件不同的第二组照明条件下，光致抗蚀剂层中的隔离区域通过不同于第一掩模的第二掩模曝光。 曝光的光致抗蚀剂层被图案化，然后使用图案化的光致抗蚀剂层作为掩模来对第一层进行图案化。
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公开(公告)号：US06979837B2
公开(公告)日：2005-12-27
申请号：US10848679
申请日：2004-05-19
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0078
摘要： The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.
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公开(公告)号：US06815359B2
公开(公告)日：2004-11-09
申请号：US09819552
申请日：2001-03-28
IPC分类号： H01L21302
CPC分类号： H01L21/0273 , H01L21/28123 , H01L21/32139
摘要： An integrated circuit fabrication process is disclosed herein. The process includes exposing a photoresist layer to a plasma, and transforming the top surface and the side surfaces of the photoresist layer to form a hardened surface. The process further includes etching the substrate in accordance with the transformed feature, wherein an etch stability of the feature is increased by the hardened surface. The photoresist layer is provided at a thickness less than 0.25 &mgr;m, for use in deep ultraviolet lithography, or for use in extreme ultraviolet lithography.
摘要翻译： 本文公开了一种集成电路制造工艺。 该方法包括将光致抗蚀剂层暴露于等离子体，以及转变光致抗蚀剂层的顶表面和侧表面以形成硬化表面。 该方法还包括根据变换的特征蚀刻衬底，其中通过硬化表面增加特征的蚀刻稳定性。 光致抗蚀剂层以小于0.25μm的厚度提供，用于深紫外光刻或用于极紫外光刻。
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公开(公告)号：US06716571B2
公开(公告)日：2004-04-06
申请号：US09819343
申请日：2001-03-28
IPC分类号： G03F700
CPC分类号： H01L21/28123 , Y10S430/143
摘要： A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch rates in the vertical and horizontal directions. The modified photoresist layer is trimmed with a plasma etch. A feature included in the trimmed photoresist layer has a sub-lithographic lateral dimension.
摘要翻译： 本文公开了在集成电路中形成次光刻特征的工艺。 该方法包括在图案化和显影之后但在其用于对下面的层进行图案化之前修饰光致抗蚀剂层。 改性光致抗蚀剂层在垂直和水平方向具有不同的蚀刻速率。 用等离子体蚀刻修整修饰的光致抗蚀剂层。 修整的光致抗蚀剂层中包括的特征具有亚光刻横向尺寸。
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