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公开(公告)号：US12125799B2
公开(公告)日：2024-10-22
申请号：US17517608
申请日：2021-11-02
IPC分类号： H01L23/538 , H01L21/56 , H01L23/373 , H01L23/498
CPC分类号： H01L23/5389 , H01L21/568 , H01L23/3735 , H01L23/49861
摘要： Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.
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公开(公告)号：US12046542B2
公开(公告)日：2024-07-23
申请号：US17246056
申请日：2021-04-30
发明人： Makoto Shibuya , Makoto Yoshino , Kengo Aoya
IPC分类号： H01L23/495 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/49
CPC分类号： H01L23/49568 , H01L21/4825 , H01L21/4885 , H01L21/565 , H01L23/3114 , H01L23/49 , H01L23/49506 , H01L23/4952 , H01L23/49582
摘要： In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.
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公开(公告)号：US11942384B2
公开(公告)日：2024-03-26
申请号：US17515234
申请日：2021-10-29
IPC分类号： H01L23/31 , H01L23/00 , H01L23/495
CPC分类号： H01L23/3107 , H01L23/4952 , H01L24/16 , H01L24/48 , H01L2224/16245 , H01L2224/48245
摘要： A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
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公开(公告)号：US11923320B2
公开(公告)日：2024-03-05
申请号：US17139417
申请日：2020-12-31
IPC分类号： H01L21/78 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/552
CPC分类号： H01L23/552 , H01L21/561 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/3135 , H01L23/49816 , H01L24/48 , H01L2224/48245
摘要： A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
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公开(公告)号：US20230275007A1
公开(公告)日：2023-08-31
申请号：US17683074
申请日：2022-02-28
发明人： Makoto SHIBUYA , Masamitsu Matsuura , Kengo Aoya , Anindya Poddar
IPC分类号： H01L23/495 , H01L23/31 , H01L23/00 , H01L21/56 , H01L21/48
CPC分类号： H01L23/49555 , H01L23/3107 , H01L24/48 , H01L24/85 , H01L21/565 , H01L21/4842 , H01L2224/48245 , H01L24/32 , H01L2224/32245 , H01L24/73 , H01L2224/73265
摘要： In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.
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公开(公告)号：US20230060830A1
公开(公告)日：2023-03-02
申请号：US17461423
申请日：2021-08-30
摘要： A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.
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公开(公告)号：US20220108955A1
公开(公告)日：2022-04-07
申请号：US17517608
申请日：2021-11-02
IPC分类号： H01L23/538 , H01L23/498 , H01L21/56 , H01L23/373
摘要： Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.
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公开(公告)号：US20200091076A1
公开(公告)日：2020-03-19
申请号：US16132906
申请日：2018-09-17
IPC分类号： H01L23/538 , H01L23/373 , H01L21/56 , H01L23/498
摘要： Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.
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公开(公告)号：US10580715B2
公开(公告)日：2020-03-03
申请号：US16008119
申请日：2018-06-14
发明人： Woochan Kim , Masamitsu Matsuura , Mutsumi Masumoto , Kengo Aoya , Hau Thanh Nguyen , Vivek Kishorechand Arora , Anindya Poddar
IPC分类号： H01L23/10 , H01L23/34 , H01L23/367 , H01L21/56 , H01L23/00 , H01L23/373
摘要： The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.
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