公开(公告)号：US20240027514A1

公开(公告)日：2024-01-25

申请号：US18168502

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hong Lin ,  Yu-Ting Lin ,  Mill-Jer Wang

IPC: G01R31/265

CPC classification number: G01R31/2653

Abstract: A method includes: providing a first semiconductor device including a backside interconnection structure, the first semiconductor device being formed by a semiconductor process; and generating a physical failure analysis model by an inspection process. The inspection process includes: directing an electron beam toward the frontside of the first semiconductor device; and applying an electrical signal to an electrical contact of the first semiconductor device through an electrical path that goes through a shunt board attached to a switchable interface trace bank, the electrical contact being associated with a position of the electron beam. The method further includes: generating a parameter of a revised semiconductor process according to the physical failure analysis model and the semiconductor process; and forming a second semiconductor device by the revised semiconductor process using the parameter.

公开(公告)号：US20220197132A1

公开(公告)日：2022-06-23

申请号：US17692912

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po Hsuan Li ,  Yu-Ting Lin ,  Yun-Yue Lin ,  Huai-Tei Yang

IPC: G03F1/62 ,  G03F7/20

Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.

公开(公告)号：US10468530B2

公开(公告)日：2019-11-05

申请号：US16043371

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Wang ,  Yu-Ting Lin ,  Yueh-Ching Pai ,  Shih-Chieh Chang ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/3065

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.

公开(公告)号：US10332789B2

公开(公告)日：2019-06-25

申请号：US15887819

申请日：2018-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei Chou ,  Ken-Yu Chang ,  Chun-Chieh Wang ,  Yueh-Ching Pai ,  Yu-Ting Lin ,  Yu-Wen Cheng

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L29/78 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/417 ,  C23C16/02 ,  C23C16/455

Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.