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    Extreme ultraviolet lithography system
    22.
    发明授权
    Extreme ultraviolet lithography system 有权

    公开(公告)号：US10520833B1

    公开(公告)日：2019-12-31

    申请号：US16035354

    申请日：2018-07-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

    IPC: G03B27/58 ,  G03F7/20

    Abstract: Semiconductor systems, apparatuses and methods are provided. In one embodiment, an extreme ultraviolet lithography system includes a substrate stage configured to secure a substrate at a first vertical level, wherein the substrate is deposited with a resist layer thereon; at least one electrode positioned at a second vertical level above the first vertical level; and a power source configured to apply an electric field across the at least one electrode and the substrate stage, including across a thickness of the resist layer when the substrate is secured on the substrate stage.

    Negative tone developer for extreme ultraviolet lithography
    23.
    发明授权
    Negative tone developer for extreme ultraviolet lithography 有权

    公开(公告)号：US10520820B2

    公开(公告)日：2019-12-31

    申请号：US15694222

    申请日：2017-09-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Yu Liu ,  Wei-Han Lai ,  Tzu-Yang Lin ,  Ming-Hui Weng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

    IPC: G03F7/32 ,  G03F7/16 ,  G03F7/20

    Abstract: The present disclosure provides NTD developers and corresponding lithography techniques that can overcome resolution, line edge roughness (LER), and sensitivity (RLS) tradeoff barriers particular to extreme ultraviolet (EUV) technologies, thereby achieving high patterning fidelity for advanced technology nodes. An exemplary lithography method includes forming a negative tone resist layer over a workpiece; exposing the negative tone resist layer to EUV radiation; and removing an unexposed portion of the negative tone resist layer in a negative tone developer, thereby forming a patterned negative tone resist layer. The negative tone developer includes an organic solvent having a log P value greater than 1.82. The organic solvent is an ester acetate derivative represented by R1COOR2. R1 and R2 are hydrocarbon chains having four or less carbon atoms. In some implementations, R1, R2, or both R1 and R2 are propyl functional groups, such as n-propyl, isopropyl, or 2-methylpropyl.

    Lithography Techniques for Reducing Resist Swelling
    24.
    发明申请
    Lithography Techniques for Reducing Resist Swelling 审中-公开

    公开(公告)号：US20190004430A1

    公开(公告)日：2019-01-03

    申请号：US15639033

    申请日：2017-06-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

    IPC: G03F7/40

    CPC classification number: G03F7/40 ,  G03F7/0392

    Abstract: The present disclosure provides lithography resist materials and corresponding lithography techniques for improving lithography resolution, in particular, by reducing swelling of resist layers during development. An exemplary lithography method includes performing a treatment process on a resist layer to cause cross-linking of acid labile group components of the resist layer via cross-linkable functional components, performing an exposure process on the resist layer, and performing a development process on the resist layer. In some implementations, the resist layer includes an exposed portion and an unexposed portion after the exposure process, and the treatment process reduces solubility of the unexposed portion to a developer used during the development process by increasing a molecular weight of a polymer in the unexposed portion. The treatment process is performed before or after the exposure process. The treatment process can include performing a thermal treatment and/or an electromagnetic wave treatment to heat the resist layer.

    UNDER LAYER COMPOSITION AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    26.
    发明申请
    UNDER LAYER COMPOSITION AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180277359A1

    公开(公告)日：2018-09-27

    申请号：US15468109

    申请日：2017-03-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Yu Liu ,  Chin-Hsiang Lin ,  Ching-Yu Chang ,  Ming-Hui Weng

    IPC: H01L21/027 ,  H01L21/311 ,  C09D201/06 ,  G03F7/11 ,  G03F7/16 ,  G03F7/09

    Abstract: Under layer composition and methods of manufacturing semiconductor devices are disclosed. The method of manufacturing semiconductor device includes the following steps. A layer of an under layer composition is formed, wherein the under layer composition includes a polymeric material and a cross-linker, and the cross-linker includes at least one decomposable functional group. A curing process is performed on the layer of the under layer composition to form an under layer, wherein the cross-linker is crosslinked with the polymeric material to form a crosslinked polymeric material having the at least one decomposable functional group. A patterned photoresist layer is formed over the under layer. An etching process is performed to transfer a pattern of the patterned photoresist layer to the under layer. The under layer is removed by decomposing the decomposable functional group.

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