公开(公告)号：US20230180452A1

公开(公告)日：2023-06-08

申请号：US17956102

申请日：2022-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Taegyu KANG ,  Keunnam KIM ,  Sung-Min PARK ,  Taehyun AN ,  Sanghyun LEE ,  Eunsuk JANG ,  Moonyoung JEONG ,  Euichul JEONG ,  Hyungeun CHOI

IPC: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

CPC classification number: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.

公开(公告)号：US20190287977A1

公开(公告)日：2019-09-19

申请号：US16419947

申请日：2019-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20190206877A1

公开(公告)日：2019-07-04

申请号：US16125167

申请日：2018-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Wan KIM ,  Keunnam KIM ,  Juik LEE

IPC: H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L23/535 ,  G11C8/08

Abstract: A semiconductor memory device includes a word line buried in an upper portion of a substrate and extending in a first direction, and a word line contact plug connected to the word line. An end portion of the word line includes a contact surface exposed in the first direction, and the word line contact plug is connected to the contact surface.

公开(公告)号：US20240341081A1

公开(公告)日：2024-10-10

申请号：US18388295

申请日：2023-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun LEE ,  Keunnam KIM ,  Seungmuk KIM ,  Kiseok LEE

IPC: H10B12/00 ,  G11C5/06

CPC classification number: H10B12/315 ,  G11C5/063 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device which includes a semiconductor substrate having a cell area and a peripheral area, the peripheral area including a first area and a second area adjacent to each other, first transistors on the first area, a first wiring layer on the first transistors, a first pad on the second area and a portion of the first area, a first contact plug between the first wiring layer and the first area, a second contact plug between the first pad and the first area, a second pad on the first wiring layer, a third contact plug between the second pad and the first wiring layer, and a plurality of first capacitors on the second pad and that vertically overlap the first transistors, thus reliability and electrical characteristics of the semiconductor device may be increased.

公开(公告)号：US20240268101A1

公开(公告)日：2024-08-08

申请号：US18471900

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SangJae PARK ,  Seung-Bo KO ,  Keunnam KIM ,  Jongmin KIM ,  Hui-Jung KIM ,  Taejin PARK ,  Chan-Sic YOON ,  Kiseok LEE ,  Myeong-Dong LEE ,  Hongjun LEE

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/34 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes first and second active patterns extending in a first direction and being adjacent to each other in a second direction, the first and second active patterns, each of which includes first and second edges spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge of the first active pattern, a second storage node pad and a second storage node contact sequentially provided on the second edge of the second active pattern, and a fence pattern between the first and the second storage node contacts. Bottom and top surfaces of the first storage node contact are located at first and second levels, respectively. In a third direction, a width of the fence pattern at the first level is less than a width of the fence pattern at the second level.

公开(公告)号：US20240006250A1

公开(公告)日：2024-01-04

申请号：US18150324

申请日：2023-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunnam KIM ,  Kiseok LEE ,  Byeongjoo KU

IPC: H01L21/66 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L22/20 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76879 ,  H01L21/76816

Abstract: Disclosed is a semiconductor fabrication method comprising forming a first conductive structure and a second conductive structure, measuring a misalignment value between the first conductive structure and the second conductive structure, based on the measured misalignment value selecting a reticle from a set of reticles, and using the selected reticle to form a connection conductive structure that electrically connects the first conductive structure to the second conductive structure.

公开(公告)号：US20230157003A1

公开(公告)日：2023-05-18

申请号：US17828298

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Yongseok KIM ,  Hui-Jung KIM ,  Min Hee CHO ,  Yoosang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10873 ,  H01L27/10897

Abstract: A semiconductor memory device including a stack structure including layer groups that are vertically stacked on a substrate and including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and a vertically extending bit line on one side of the stack structure, wherein the word line of each of the layer groups extends in a first direction parallel to a top surface of the substrate, the layer groups include first and second layer groups that are sequentially stacked, the channel layer is below the word line of the first layer group, the channel layer is above the word line of the second layer group, and the bit line includes a first protrusion portion connected to the channel layer of the first layer group; and a second protrusion portion connected to the channel layer of the second layer group.

公开(公告)号：US20230157002A1

公开(公告)日：2023-05-18

申请号：US17745960

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10897 ,  H01L27/10873

Abstract: A semiconductor memory device including a stack including layer groups vertically stacked on a substrate, each of the layer groups including a word line, a lower channel layer, an upper channel layer, and a data storing element electrically connected to the lower channel layer and the upper channel layer; and a bit line at a side of the stack, the bit line extending vertically, wherein the bit line includes a protruding portion connected to the lower channel layer and the upper channel layer of each layer group, the word line of each layer group extends in a first direction parallel to a top surface of the substrate, and the word line of each layer group is sandwiched between the lower channel layer and the upper channel layer of the layer group.

公开(公告)号：US20230084388A1

公开(公告)日：2023-03-16

申请号：US17730279

申请日：2022-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Min Hee CHO

IPC: H01L29/786 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, the channel layer including an amorphous oxide semiconductor, and a width of the gate electrode being greater than a width of the channel layer, a first conductive electrode connected to a first side surface of the channel layer, and a second conductive electrode connected to a second side surface of the channel layer.

公开(公告)号：US20230055147A1

公开(公告)日：2023-02-23

申请号：US17741701

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.