公开(公告)号：US20240429214A1

公开(公告)日：2024-12-26

申请号：US18820569

申请日：2024-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Heewon KIM ,  Sechul PARK ,  Jongho PARK ,  Junyoung PARK

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

公开(公告)号：US20240187002A1

公开(公告)日：2024-06-06

申请号：US18350606

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwook LEE ,  Joohwan KIM ,  Junyoung PARK ,  Jindo BYUN ,  Eunseok SHIN ,  Junghwan CHOI

IPC: H03L7/081 ,  G11C7/22 ,  H03K5/135

CPC classification number: H03L7/0812 ,  G11C7/222 ,  H03K5/135

Abstract: A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.

公开(公告)号：US20240015597A1

公开(公告)日：2024-01-11

申请号：US18472950

申请日：2023-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junsu CHOI ,  Junyoung PARK ,  Hyeonu CHOI ,  Jeongyong MYOUNG ,  Junghun LEE

IPC: H04W28/24 ,  H04W74/08

CPC classification number: H04W28/24 ,  H04W74/0816 ,  H04W84/12

Abstract: A method and an apparatus for controlling communication parameters in multiple communication are provided. The apparatus includes a memory and a processor operatively coupled to the memory, wherein the memory includes instructions for allowing the processor to, set a first service period duration and a first wake interval, related to first communication, on the basis of the quality of service of the first communication, set a second service period duration and a second wake interval, related to second communication, on the basis of the quality of service of the second communication when a second communication connection having a frequency overlapping with that of the first communication is detected, determine whether the time difference between the first wake interval and the second wake interval occurs, and change, on the basis of the determination result, the first wake interval and the second wake interval to correspond to each other.

公开(公告)号：US20220385287A1

公开(公告)日：2022-12-01

申请号：US17751148

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung PARK ,  Joohwan KIM ,  Jindo BYUN ,  Eunseok SHIN ,  Hyunyoon CHO ,  Youngdon CHOI ,  Junghwan CHOI

IPC: H03K17/693 ,  H03K19/20

Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

公开(公告)号：US20200265627A1

公开(公告)日：2020-08-20

申请号：US16795794

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghwan SEO ,  Hyejin KANG ,  Junho AN ,  Minsheok CHOI ,  Yonggyoo KIM ,  Junyoung PARK ,  Chanhee YOON ,  Wooyong LEE ,  Jonghoon WON

IPC: G06T13/40 ,  G06K9/00 ,  G06T7/73 ,  H04N5/232

Abstract: An electronic device and method are disclosed. The electronic device includes a camera, a display, and a processor. The processor implements the method, including capturing an image using a camera of the electronic device for animation of an avatar, the image including at least a part of a face of a user, analyzing, by a processor, a portion of the image including the at least the part of the face to determine whether an entirety of the face is captured within the image, and selecting a primary image or an alternative image for display of the avatar based on the determination, including: displaying the avatar on a display of the electronic device using the alternative image when less than the entirety of the face is captured within the image.