公开(公告)号：US12040299B2

公开(公告)日：2024-07-16

申请号：US18218909

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkyu Lee ,  Jingu Kim ,  Yongkoon Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L23/3121 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/081 ,  H01L2224/13024 ,  H01L2224/221 ,  H01L2224/48227 ,  H01L2225/0651

Abstract: A semiconductor package includes a support member, a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface respectively, a lower redistribution wiring layer covering the second surface of the support member and including first redistribution wirings electrically connected to chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member respectively, and an upper redistribution wiring layer covering the first surface of the support substrate, and including second redistribution wirings electrically connected to the vertical connection structures and a thermal pattern provided on the exposed backside surface of the semiconductor chip.

公开(公告)号：US20240213113A1

公开(公告)日：2024-06-27

申请号：US18343011

申请日：2023-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Eok Kwon ,  Wooyoung Kim ,  Jingu Kim ,  Sangkyu Lee

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/3675 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/16

Abstract: A semiconductor package includes: a first redistribution layer; at least one lower die on the first redistribution layer; a first through-via on the first redistribution layer; a first molding material that molds the first redistribution layer, the at least one lower die, and the first through-via; a second redistribution layer on the at least one lower die, the first through-via, and the first molding material; at least one upper die on the second redistribution layer and having a thickness between 1.2 and 1.7 times, including endpoints, greater than a thickness of the at least one lower die; a second through-via on the second redistribution layer; a second molding material that molds the second redistribution layer, the at least one upper die, and the second through-via; and a heat dissipation member on the at least one upper die and the second through-via, wherein the heat dissipation member contacts the second through-via.

公开(公告)号：US11973042B2

公开(公告)日：2024-04-30

申请号：US17867388

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jingu Kim ,  Shanghoon Seo ,  Sangkyu Lee ,  Jeongho Lee

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/3511

Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post' and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.

公开(公告)号：US20230163038A1

公开(公告)日：2023-05-25

申请号：US18099663

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingu Kim ,  Sangkyu Lee ,  Yongkoon Lee ,  Seokkyu Choi

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/105 ,  H01L24/20 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor package includes a connection layer, a semiconductor chip disposed at a center portion of the connection layer, an adhesive layer disposed on the semiconductor chip, a heat spreader layer disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip. A width of the adhesive layer is the same as a width of the semiconductor chip, and a width of the heat spreader layer is less than the width of the adhesive layer.