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公开(公告)号：US11817067B2
公开(公告)日：2023-11-14
申请号：US17221461
申请日：2021-04-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Unki Park , Minsik Kim , Hyeonsu Park , Jonghyuk Lee , Hyunwook Lim , Woohyuk Jang
CPC classification number: G09G5/393 , G04G9/0082 , G09G5/395 , G09G2330/023 , G09G2360/06
Abstract: A display driving circuit for driving a display panel, including a first memory configured to store main image data received from outside of the display driving circuit; a second memory configured to store first additional image data in a normal mode, and to store second additional image data in an Always On Display (AOD) mode having lower power consumption than the normal mode; a normal mode controller configured to operate in the normal mode according to the first additional image data stored in the second memory; and an AOD mode controller configured to operate in the AOD mode according to the main image data stored in the first memory and the second additional image data stored in the second memory.
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公开(公告)号：US20230137060A1
公开(公告)日：2023-05-04
申请号：US17807237
申请日：2022-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinyong Park , Hongki Kwon , Taewoo Kim , Hyeonsu Park , Hyunwook Lim , Hojun Chung
Abstract: A display driver integrated circuit includes a frame buffer, a plurality of image processing circuits and an image processing controller. The frame buffer sequentially stores a plurality of frame data received from a host processor. Each of the plurality of frame data includes a plurality of data slices. The image processing circuits perform image signal processing operations, respectively, on ones of the data slices that are included in a respective one of the plurality of frame data and which are sequentially retrieved from the frame buffer. The image processing controller bypasses at least one of the image processing circuits by applying a bypass control signal to the image processing circuits based on a first plurality of data slices included in a first one of the plurality of frame data and a second plurality of data slices included in a second one of the plurality of frame data.
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公开(公告)号：US11632228B2
公开(公告)日：2023-04-18
申请号：US17476782
申请日：2021-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungpil Lim , Kyungho Ryu , Kilhoon Lee , Hyunwook Lim
Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
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公开(公告)号：US11594181B2
公开(公告)日：2023-02-28
申请号：US17492985
申请日：2021-10-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Unki Park , Minsik Kim , Hyeonsu Park , Hyunwook Lim , Woohyuk Jang
IPC: G09G3/3258
Abstract: A display driving circuit for driving a display panel includes a control logic that adjusts brightness of a first partial area by adjusting pixel data values included in partial image data to be displayed on the first partial area of the display panel based on received brightness control information, and a data driver that generates image signals by digital-analog conversion of pixel data values provided from the control logic, the data driver providing the image signals to the display panel.
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公开(公告)号：US11133920B2
公开(公告)日：2021-09-28
申请号：US16878728
申请日：2020-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungpil Lim , Kyungho Ryu , Kilhoon Lee , Hyunwook Lim
Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
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Patent Agency Ranking
公开(公告)号：US10763866B2
公开(公告)日：2020-09-01
申请号：US16511733
申请日：2019-07-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyungho Ryu , Hansu Pae , Kilhoon Lee , Jaeyoul Lee , Jung-Pil Lim , Hyunwook Lim
Abstract: An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.
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公开(公告)号：US12288495B2
公开(公告)日：2025-04-29
申请号：US18238885
申请日：2023-08-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seong-Young Ryu , Sunkwon Kim , Wangsuk Sung , Uijong Song , Yilho Lee , Heejin Lee , Hyunwook Lim
IPC: G09G3/20
Abstract: A display device is provided. The display device includes: a pixel array including pixels connected to gate lines and source lines; and a driving circuit configured to: apply gate signals to the gate lines and provide data signals to the source lines during a first scan period such that horizontal periods of the gate signals do not overlap each other, and apply the gate signals to first gate lines, of the gate lines, connected to pixels in a first area of the pixel array in a different manner from second gate lines, of the gate lines, connected to pixels in a second area of the pixel array for a portion of a second scan period, provide the data signals to the source lines, and maintain a low-biased state or an off state for a remaining portion of the second scan period.
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公开(公告)号：US12132491B2
公开(公告)日：2024-10-29
申请号：US18074775
申请日：2022-12-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyungho Ryu , Yongil Kwon , Kilhoon Lee , Jung-Pil Lim , Hyunwook Lim
CPC classification number: H03L7/091 , G06F1/10 , G11C7/222 , H04L7/0037 , H04L7/0087 , H04L7/033
Abstract: The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.
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公开(公告)号：US12106736B2
公开(公告)日：2024-10-01
申请号：US17807237
申请日：2022-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinyong Park , Hongki Kwon , Taewoo Kim , Hyeonsu Park , Hyunwook Lim , Hojun Chung
CPC classification number: G09G5/393 , G09G3/3696 , G09G2330/021 , G09G2360/18
Abstract: A display driver integrated circuit includes a frame buffer, a plurality of image processing circuits and an image processing controller. The frame buffer sequentially stores a plurality of frame data received from a host processor. Each of the plurality of frame data includes a plurality of data slices. The image processing circuits perform image signal processing operations, respectively, on ones of the data slices that are included in a respective one of the plurality of frame data and which are sequentially retrieved from the frame buffer. The image processing controller bypasses at least one of the image processing circuits by applying a bypass control signal to the image processing circuits based on a first plurality of data slices included in a first one of the plurality of frame data and a second plurality of data slices included in a second one of the plurality of frame data.
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公开(公告)号：US20240112650A1
公开(公告)日：2024-04-04
申请号：US18199163
申请日：2023-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Yun PARK , Alankyongho Kim , Hyunwook Lim , Yongil Kwon
IPC: G09G5/39
CPC classification number: G09G5/39 , G09G2300/0452 , G09G2310/0297 , G09G2340/16 , G09G2356/00
Abstract: The present disclosure provides transmitter circuits and display devices including the same. In some embodiments, the transmitter circuit includes a run length detector, a modifier, and a scrambler. The run length detector is configured to derive position information indicating a first input data related to a threshold run length from among a plurality of input data in a predetermined bit unit, when a run length of first scrambled data for the first input data meets or exceeds the threshold run length in the predetermined bit unit. The modifier is configured to generate modified input data by inverting at least one bit of the first input data based on the position information. The scrambler is configured to receive the modified input data from the modifier, and generate second scrambled data by scrambling the modified input data with scrambling information.
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