公开(公告)号：US09287265B2

公开(公告)日：2016-03-15

申请号：US14295333

申请日：2014-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Kook Park ,  Hongsoo Kim ,  Won-Chul Jang

IPC: H01L27/105 ,  H01L27/06 ,  H01L23/485

CPC classification number: H01L27/105 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate with an active region defined by a device isolation layer. A word line extends over the active region in a first direction, and a plurality of interconnections extends over the word line in a second direction perpendicular to the first direction. A contact pad is disposed between and spaced apart from the word line and the plurality of interconnections, extending in the first direction to overlap the plurality of interconnections and the active region when viewed from a plan view. A lower contact plug electrically connects the contact pad to the active region. An upper contact plug electrically connects the contact pad to one of the plurality of interconnections.

Abstract translation: 半导体器件包括具有由器件隔离层限定的有源区的衬底。 字线在第一方向上在有源区域上延伸，并且多个互连在垂直于第一方向的第二方向上在字线上延伸。 接触垫设置在字线和多个互连之间并与之隔开的多个互连，当从平面图观察时，沿第一方向延伸以与多个互连和有源区重叠。 下接触插头将接触垫电连接到有源区域。 上接触插头将接触垫电连接到多个互连中的一个。

公开(公告)号：US20150261905A1

公开(公告)日：2015-09-17

申请号：US14576695

申请日：2014-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HunKook LEE ,  Hongsoo Kim ,  Juyeon Lee

IPC: G06F17/50 ,  H01L21/8234 ,  H01L29/06 ,  G03F1/00 ,  H01L27/088

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F17/5081 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0653

Abstract: Methods of preparing layouts for semiconductor devices and semiconductor devices fabricated using the layouts are provided. Preparing the layouts for semiconductor devices may include disposing assistant patterns near a main gate pattern that is provided on a weak active pattern. The weak active pattern may be, for example, an outermost one of active patterns and may be one expected to have an increased width during a fabrication process.

Abstract translation: 提供了使用布局制造的半导体器件和半导体器件布局的方法。 准备半导体器件的布局可以包括将辅助图案布置在提供在弱有源图案上的主栅格图案附近。 弱活性图案可以是例如活性图案中最外面的一种，并且可以是预期在制造过程中具有增加的宽度的活性图案。