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21.发明授权Three-dimensional semiconductor memory device having compensating data skewing according to interlayer timing delay and method of de-skewing data therein 有权具有根据层间定时延迟的补偿数据偏移的三维半导体存储器件以及其中的数据失真的方法公开(公告)号：US08917564B2
公开(公告)日：2014-12-23
申请号：US13937367
申请日：2013-07-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hak-Soo Yu , Sang-Bo Lee , Hong-Sun Hwang , Dong-Hyun Sohn
IPC: G11C7/00 , G11C5/02 , G11C5/06 , G11C8/14 , G11C8/18 , G11C13/00 , G11C29/02 , G11C29/50 , G11C7/22
CPC classification number: G11C5/02 , G11C5/063 , G11C7/222 , G11C8/14 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0061 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C2213/71
Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.
Abstract translation: 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。
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22.发明申请Semiconductor Devices Having a Three Dimensional Stacked Structure and Methods of De-Skewing Data Therein 有权具有三维堆叠结构的半导体器件及其中的数据偏移方法公开(公告)号：US20130329478A1
公开(公告)日：2013-12-12
申请号：US13937367
申请日：2013-07-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hak-Soo Yu , Sang-Bo LEE , Hong-Sun HWANG , Dong-Hyun SOHN
CPC classification number: G11C5/02 , G11C5/063 , G11C7/222 , G11C8/14 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0061 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C2213/71
Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.
Abstract translation: 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。
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