公开(公告)号：US10566529B2

公开(公告)日：2020-02-18

申请号：US15862926

申请日：2018-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hyun Jeong ,  Jin-Woo Lee ,  Gwan-Hyeob Koh ,  Dae-Hwan Kang

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

公开(公告)号：US10388859B2

公开(公告)日：2019-08-20

申请号：US15856256

申请日：2017-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Shik Kim ,  Jeong-Heon Park ,  Gwan-Hyeob Koh

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L29/417

Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.

公开(公告)号：US10224086B2

公开(公告)日：2019-03-05

申请号：US15816810

申请日：2017-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Shik Kim ,  Suk-Soo Pyo ,  Gwan-Hyeob Koh

IPC: G11C7/04 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08

Abstract: A memory device includes at least one reference cell and multiple memory cells. A method of operating the memory device may include detecting a temperature of the memory device and controlling a level of a first read signal applied to the at least one reference cell in accordance with a result of the detecting of the temperature. The method may also include comparing a first sensing value sensed by applying the first read signal to the at least one reference cell with a second sensing value sensed by applying a second read signal to a selected memory cell among the multiple memory cells.

公开(公告)号：US20180351080A1

公开(公告)日：2018-12-06

申请号：US16045824

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-HOON BAK ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

公开(公告)号：US10141373B2

公开(公告)日：2018-11-27

申请号：US15387751

申请日：2016-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Song-Yi Kim ,  Jae-Kyu Lee ,  Dae-Hwan Kang ,  Gwan-Hyeob Koh

IPC: H01L27/24 ,  H01L45/00

Abstract: A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern. Each of the plurality of second conductive patterns extends in a second direction crossing the first direction.

公开(公告)号：US10109676B2

公开(公告)日：2018-10-23

申请号：US15293771

申请日：2016-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Bak ,  Woo-Jin Kim ,  Mina Lee ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.

公开(公告)号：US10062840B2

公开(公告)日：2018-08-28

申请号：US15332042

申请日：2016-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Rie Sim ,  Dae-Hwan Kang ,  Gwan-Hyeob Koh

IPC: H01L45/00 ,  H01L43/08 ,  H01L43/10 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2427 ,  H01L27/2481 ,  H01L43/08 ,  H01L43/10 ,  H01L45/04 ,  H01L45/06 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675

Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.

公开(公告)号：US20170309683A1

公开(公告)日：2017-10-26

申请号：US15633029

申请日：2017-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYU-RIE SIM ,  Gwan-Hyeob Koh ,  Dae-Hwan Kang

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.