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    Electronic apparatus and control method thereof
    21.
    发明授权
    Electronic apparatus and control method thereof 有权

    公开(公告)号：US11153575B2

    公开(公告)日：2021-10-19

    申请号：US16292655

    申请日：2019-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

    Inventor： Hyunseung Lee ,  Donghyun Kim ,  Youngsu Moon ,  Taegyoung Ahn ,  Yoonsik Kim ,  Jaewoo Park ,  Jae Woong Soh ,  Nam Ik Cho ,  Byeongyong Ahn

    IPC: H04N19/176 ,  G06K9/40 ,  G06N3/02 ,  H04N19/137

    Abstract: An electronic apparatus is provided. The electronic apparatus includes a storage configured to store a compression rate network model configured to determine a compression rate applied to an image block from among a plurality of compression rates, and a plurality of compression noise removing network models configured to remove compression noise for each of the plurality of compression rates, and a processor configured to: obtain a compression rate of each of a plurality of image blocks included in a frame of a decoded moving picture based on the compression rate network model, obtain the compression rate of the frame based on the plurality of obtained compression rates, and remove compression noise of the frame based on a compression noise removing network model corresponding to the compression rate of the frame from among the plurality of compression noise removing network models. The compression rate network model can be obtained by learning image characteristics of a plurality of restored image blocks corresponding to each of the plurality of compression rates through a first artificial intelligence algorithm, and the plurality of restored image blocks can be generated by encoding a plurality of original image blocks, and decoding the encoded plurality of original image blocks, and the plurality of compression noise removing network models can be obtained by learning a relation between the plurality of original image blocks and the plurality of restored image blocks through a second artificial intelligence algorithm.

    Semiconductor devices including stacked semiconductor chips
    26.
    发明授权
    Semiconductor devices including stacked semiconductor chips 有权

    公开(公告)号：US10199355B2

    公开(公告)日：2019-02-05

    申请号：US15358579

    申请日：2016-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Donghyun Kim ,  DooWon Kwon

    IPC: H01L25/065 ,  H01L23/00 ,  H01L27/146 ,  F01P7/04 ,  F01P11/20

    Abstract: A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.

    Semiconductor device
    27.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10128154B2

    公开(公告)日：2018-11-13

    申请号：US15674185

    申请日：2017-08-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heedon Jeong ,  Jae Yup Chung ,  Heesoo Kang ,  Donghyun Kim ,  Sanghyuk Hong ,  Soohun Hong

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L27/088

    Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

    Stack-type semiconductor device
    28.
    发明授权
    Stack-type semiconductor device 有权

    公开(公告)号：US09859321B2

    公开(公告)日：2018-01-02

    申请号：US15333382

    申请日：2016-10-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghyun Kim ,  Doowon Kwon

    IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146

    CPC classification number: H01L27/14634 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/1469

    Abstract: A stack-type semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower interconnection on the lower substrate, a lower pad on the lower interconnection, and a lower interlayer insulating layer covering side surfaces of the lower interconnection and the lower pad. The upper device includes an upper substrate, an upper interconnection under the upper substrate, an upper pad under the upper interconnection, and an upper interlayer insulating layer covering side surfaces of the upper interconnection and the upper pad. Each of the pads has a thick portion and a thin portion. The thin portions of the pads are bonded to each other, the thick portion of the lower pad contacts the bottom of the upper interlayer insulating layer, and the thick portion of the upper pad contacts the top of the lower interlayer insulating layer.

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