公开(公告)号：US20210028281A1

公开(公告)日：2021-01-28

申请号：US16806629

申请日：2020-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhoon Kim ,  Dongmyoung Kim ,  Kanghun Moon ,  Hyunkwan Yu ,  Sanggil Lee ,  Seunghun Lee ,  Sihyung Lee ,  Choeun Lee ,  Edward Namkyu Cho ,  Yang Xu

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.

公开(公告)号：US10319859B2

公开(公告)日：2019-06-11

申请号：US15844863

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  JinBum Kim ,  Kang Hun Moon ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Yang Xu

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US09252244B2

公开(公告)日：2016-02-02

申请号：US14498996

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum Kim ,  Seong Hoon Jeong ,  Jeon Il Lee ,  Seokhoon Kim ,  Kwan Heum Lee ,  Choeun Lee ,  Yu-Jin Pyo

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/161 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/12

CPC classification number: H01L29/66795 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.

Abstract translation: 本发明构思提供制造半导体器件的方法。 该方法包括图案化衬底以形成有源图案，形成与有源图案相交的栅极图案，在栅极图案的侧壁上形成栅极间隔物，形成覆盖栅极图案的上部区域的生长抑制层，以及形成 源极/漏极在栅极图案的相对的第一和第二侧。