公开(公告)号：US10170502B2

公开(公告)日：2019-01-01

申请号：US15380596

申请日：2016-12-15

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang Jeong ,  Hyun Min Cho ,  Su Bin Bae ,  Shin Il Choi ,  Sang Gab Kim

IPC: H01L27/12 ,  H01L29/417 ,  H01L21/311 ,  G02F1/1368 ,  H01L27/32

Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

公开(公告)号：US10096716B2

公开(公告)日：2018-10-09

申请号：US15271504

申请日：2016-09-21

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang Jeong ,  Hyun Min Cho ,  Su Bin Bae ,  Shin Il Choi

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L27/12

Abstract: A thin film transistor array panel includes a substrate; a data line disposed on the substrate; a buffer layer disposed on the substrate and spaced apart from the data line in a plan view; a thin film transistor disposed on the buffer layer, the thin film transistor including an oxide semiconductor layer; and a pixel electrode connected to the thin film transistor.

公开(公告)号：US09704896B2

公开(公告)日：2017-07-11

申请号：US15004392

申请日：2016-01-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Duk-Sung Kim ,  Shin Il Choi ,  Su Bin Bae ,  Yu-Gwang Jeong

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: H01L27/1259 ,  G02F1/1333 ,  G02F1/133345 ,  G02F1/133516 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/134372 ,  G02F2001/136222 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

Abstract: A manufacturing method includes forming a gate member and a common electrode line on a substrate. A gate insulating layer is formed on the gate member and the common electrode line. A semiconductor member and a data member are formed on the gate insulating layer. A first passivation layer is formed on the semiconductor member and the data member. A plurality of color filters is formed on the first passivation layer. A conductor layer and a second passivation layer are formed on the plurality of color filters. A first contact hole exposes a common electrode. A second contact hole exposes the drain electrode. The first and second contact holes are formed by a photolithography process. A pixel electrode connected to the drain electrode is formed through the first contact hole. A connecting member connected to the common electrode line and the common electrode is formed through the second contact hole.