Abstract:
A display apparatus includes a display panel, a first driver and a second driver. The display panel includes a plurality of gate lines and a plurality of data lines. The display panel is configured to display an image based on input image data. The first driver is configured to output compensating gate signals having the same timing to the gate lines during a first period and scan gate signals having different timings to the gate lines during a second period. The second driver is configured to apply a compensating data voltage corresponding to a compensating grayscale value to the data lines during the first period and a target data voltage corresponding to a target grayscale value to the data lines during the second period.
Abstract:
A display apparatus includes a display panel, a gate driving part, a data driving part and a voltage providing part. The display panel displays an image, and includes gate lines and data lines. The gate driving part outputs gate signals to the gate lines. The data driving part outputs data signals to the data lines through data channels, and outputs a dummy data signal through a dummy data channel adjacent to a side of the display panel. The voltage providing part provides a driving voltage to the data driving part, receives the dummy data signal, and controls the driving voltage provided to the data driving part based on a voltage difference of the dummy data signal according to a time of the dummy data signal.
Abstract:
A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal.
Abstract:
A display panel driving apparatus includes an image pattern analyzing part, a clock signal generating part and a data driving part. The image pattern analyzing part is configured to analyze an image pattern of an image data. The clock signal generating part is configured to generating a clock signal having a different pulse width according to the image pattern of an image data. The data driving part is configured to drive a data line of a display panel in response to the clock signal. Thus, power consumption and heating of the data driving part may be decreased.
Abstract:
A liquid crystal display having data driving apparatus comprising first and second output switches, a charge sharing line, and first and second charge sharing switches. The first output switch switches an electrical connection between a first amplifier providing a positive gradation voltage and a first data line in response to a control signal. The second output switch switches an electrical connection between a second amplifier providing a negative gradation voltage and a second data line in response to the control signal. The first charge sharing switch switches an electrical connection between the first data line and the charge sharing line in response to the control signal. The second charge sharing switch switches an electrical connection between the second data line and the charge sharing line in response to the control signal.
Abstract:
Provided is a display device including a display panel including a plurality of first pads, and a plurality of second pads spaced apart from the first pads, a first circuit board including first circuit pads respectively bonded to the first pads, a first driving chip electrically connected to the first circuit pads, and a first heat radiation member, and a second circuit board including second circuit pads respectively bonded to the second pads, and a second driving chip electrically connected to the second circuit pads, wherein the first heat radiation member overlaps the first driving chip and the second driving chip.
Abstract:
A gate driving circuit includes a shift register configured to generate a plurality of output signals based on at least one clock signal, a plurality of output buffers configured to generate a plurality of gate signals by amplifying the output signals and to sequentially output the gate signals to a plurality of gate lines in a display panel, a detector configured to sequentially sense the gate signals and to compare each of the gate signals to a reference voltage, and a dummy output buffer configured to be coupled between the shift register and a gate line of the gate lines instead of an output buffer of the output buffers when a voltage level of a corresponding gate signal from the output buffers is less than a voltage level of the reference voltage.
Abstract:
A liquid crystal display device, including: pixels; data lines and scan lines coupled to the pixels; and a driver configured to supply a scan signal to the scan lines, and supply a data voltage to the data lines. The data lines include first to third data lines, to which a data voltage having a positive polarity is supplied, and which are adjacent to each other, and fourth to sixth data lines, to which a data voltage having a negative polarity is supplied, and which are adjacent to each other.
Abstract:
A display apparatus includes a display panel, a gate driving part, and a data driving part. The display panel is configured to display an image, and includes a gate line and data lines. The gate driving part is configured to output a gate signal to the gate line. The data driving part includes a plurality of data driving integrated circuit parts. Each of the plurality of data driving integrated circuit parts includes channels, configured to output data signals to the data lines, and a dummy data channel. A sensing pin, configured to receive the gate signal, is formed in each dummy data channel.
Abstract:
Disclosed is a display apparatus including: a display panel including pixels connected with a plurality of gate lines and a plurality of data lines; a gate driver supplying gate signals to the gate lines; and a data driver supplying data voltages to the data lines. The data driver includes a temperature measurer generating a temperature signal of the data driver.