公开(公告)号：US10419246B2

公开(公告)日：2019-09-17

申请号：US15680959

申请日：2017-08-18

Applicant: QUALCOMM Incorporated

Inventor： Ying Duan ,  Abhay Dixit ,  Shih-Wei Chou ,  Jing Wu ,  Harry Dang

IPC: H04L25/02 ,  G01R31/317 ,  H03K5/135 ,  H04B3/462 ,  H04L7/00 ,  H04L25/14 ,  H04L25/49 ,  H04L23/00 ,  H04B3/54 ,  H04L1/20 ,  H04L7/04 ,  H04L25/03 ,  G06F13/42

Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of calibration includes configuring a 3-phase signal to include a high frequency component and a low frequency component during a calibration period, and transmitting a version of the 3-phase signal on each wire of a 3-wire interface. The version of the 3-phase signal transmitted on each wire is out-of-phase with the versions of the 3-phase signal transmitted on each of the other wires of the 3-wire interface. The 3-phase signal may be configured to enable a receiver to determine certain operating parameters of the 3-wire interface.

公开(公告)号：US10333690B1

公开(公告)日：2019-06-25

申请号：US15971016

申请日：2018-05-04

Applicant: QUALCOMM Incorporated

Inventor： Ying Duan ,  Abhay Dixit ,  Shih-Wei Chou ,  Chulkyu Lee

IPC: H04L7/033 ,  H04L7/00 ,  G09G5/00 ,  H04L25/49

Abstract: Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.

公开(公告)号：US10313068B1

公开(公告)日：2019-06-04

申请号：US15961687

申请日：2018-04-24

Applicant: QUALCOMM Incorporated

Inventor： Yasser Ahmed ,  Ying Duan

IPC: H04B3/46 ,  H04L1/20

Abstract: Methods, apparatus, and systems for monitoring and measuring signal characteristics for signals received over a multi-wire, multi-phase interface are disclosed. Signals present on each line of a 3-line communication interface are sampled using auxiliary samplers having a programmable time delay to delay the sampled signal by a set time, as well as a programmable voltage offset. The auxiliary sampler outputs are compared with direct line samples of signals on each of the three lines to generate error signals. From this comparison, an array of error signal data occurring over a particular sampling period may be generated. In turn, waveform characteristics can be determined from the error signal data, such as an eye-pattern. Furthermore, skew measurement may further be effectuated using the auxiliary samplers but determining the time difference of when the error signals of the different wires cross a predetermined threshold.

公开(公告)号：US10033519B2

公开(公告)日：2018-07-24

申请号：US15348290

申请日：2016-11-10

Applicant: QUALCOMM Incorporated

Inventor： Ying Duan ,  Yasser Ahmed ,  Abhay Dixit ,  Harry Huy Dang ,  Jing Wu

IPC: H04L29/06 ,  H04L7/00

Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.