公开(公告)号：US20160285453A1

公开(公告)日：2016-09-29

申请号：US14957188

申请日：2015-12-02

Applicant: QUALCOMM Incorporated

Inventor： Stephen Clifford Thilenius ,  Patrick Isakanian ,  Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  LuVerne Ray Peterson

IPC: H03K19/0175 ,  H03K5/14

CPC classification number: H03K19/017518 ,  G11C7/1057 ,  H03K5/14 ,  H03K19/018507

Abstract: In one embodiment, a system comprises a pre-driver circuit and a driver. The pre-driver circuit is powered by a first supply voltage, and configured to output a pre-drive signal. The driver comprises a pull-up NMOS transistor having a drain coupled to a second supply voltage, and a source coupled to an output of the driver, wherein the second supply voltage is lower than the first supply voltage by at least a threshold voltage of the pull-up NMOS transistor. The driver also comprises a drive circuit coupled to a gate of the pull-up NMOS transistor, wherein the drive circuit is configured to receive the pre-drive signal and to drive the gate of the pull-up NMOS transistor with a voltage approximately equal to the first supply voltage to drive the output of the driver to a high state depending on a logic state of the pre-drive signal.

Abstract translation: 在一个实施例中，系统包括预驱动器电路和驱动器。 预驱动器电路由第一电源电压供电，并且被配置为输出预驱动信号。 驱动器包括具有耦合到第二电源电压的漏极的上拉NMOS晶体管和耦合到驱动器的输出的源，其中第二电源电压低于第一电源电压至少一个阈值电压 上拉式NMOS晶体管。 驱动器还包括耦合到上拉NMOS晶体管的栅极的驱动电路，其中驱动电路被配置为接收预驱动信号并且驱动上拉NMOS晶体管的栅极，其电压近似等于 根据预驱动信号的逻辑状态，第一电源电压将驱动器的输出驱动到高电平状态。

公开(公告)号：US09337807B2

公开(公告)日：2016-05-10

申请号：US14503090

申请日：2014-09-30

Applicant: QUALCOMM Incorporated

Inventor： Timothy Mowry Hollis ,  Thomas Clark Bryan ,  Mark Wayland

IPC: H03K3/00 ,  H03K3/011 ,  G11C11/4096

CPC classification number: H03K3/011 ,  G11C11/4096 ,  H03K19/0005 ,  H03K19/00384 ,  H03K19/018585

Abstract: Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed. Settings that result from the calibration are referred to as calibration codes. The output driver circuit includes multiple pull-up elements that are enabled or disabled to produce a desired output impedance when the output is high and multiple pull-down elements that are enabled or disabled to produce the desired output impedance when the output is low. The number of pull-up elements that are enabled and the number of pull-down elements that are enabled is set by calibration. The results of the calibration (i.e., the number of enabled elements for the pull-up and the number of enabled elements for the pull-down) are used to set controls for an amount of pre-emphasis and/or to set controls for output slew rates.

Abstract translation: 公开了基于来自校准驱动电路的输出阻抗的信息来均衡输出驱动器电路的系统和方法。 由校准产生的设置称为校准代码。 输出驱动器电路包括多个上拉元件，其在输出为高电平时使能或禁止产生期望的输出阻抗，并且当输出为低电平时启用或禁用以产生所需输出阻抗的多个下拉元件。 启用的上拉元件数量和启用的下拉元件数量通过校准设置。 校准的结果（即，上拉的使能元件数量和下拉使能元件的数量）用于设置预加重量的控制和/或设置控制输出 压摆率。

公开(公告)号：US09244875B1

公开(公告)日：2016-01-26

申请号：US14335712

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Tin Tin Wee ,  Thomas Clark Bryan

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4072 ,  G06F13/4208

Abstract: Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus.

Abstract translation: 提供了数据总线反转（DBI）的电路和方法。 在一个示例中，DBI位的紧接之前的值会影响DBI位的下一个值。 具体地说，在某些情况下，DBI位的值被保持到DBI位的紧前一个值，以限制数据总线上的转换总数。

公开(公告)号：US20160020759A1

公开(公告)日：2016-01-21

申请号：US14335681

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Stephen Knol ,  Gregory Francis Lynch ,  Tin Tin Wee ,  LuVerne Ray Peterson ,  Yue Li

IPC: H03K5/15 ,  H01L23/538

CPC classification number: H03K5/15013 ,  G06F1/10 ,  G11C7/22 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract translation: 提供了芯片到芯片时钟分配的电路。 系统包括第一管芯上的传输时钟树和第二管芯上的接收时钟树。 发送时钟树和接收时钟树是相同的或非常接近相同的，所以发送时钟树上的给定位的插入延迟与对应于给定位的位的插入延迟相同 接收时钟树。 虽然在同一个时钟树中可能存在从位到位的时钟偏差，但是不同芯片上的相应位具有相同的时钟插入延迟。