公开(公告)号：US09569811B2

公开(公告)日：2017-02-14

申请号：US14316275

申请日：2014-06-26

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Tao Wang ,  Chunhui Mei ,  Gang Zhong ,  Feng Ge

IPC: G06T1/20 ,  G06T11/40 ,  G06T15/00 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/005 ,  G09G5/363 ,  G09G2340/0407 ,  G09G2360/122

Abstract: In an example, a method for rendering graphics data includes rendering pixels of a first bin of a plurality of bins, wherein the pixels of the first bin are associated with a first portion of an image, and rendering, to the first bin, one or more pixels that are located outside the first portion of the image and associated with a second, different bin of the plurality of bins. The method also includes rendering the one or more pixels associated with the second bin to the second bin, such that the one or more pixels are rendered to both the first bin and the second bin.

Abstract translation: 在一个示例中，用于渲染图形数据的方法包括渲染多个箱的第一仓的像素，其中第一仓的像素与图像的第一部分相关联，并且向第一仓中呈现一个或 更多的像素位于图像的第一部分之外并且与多个箱的第二不同仓相关联。 该方法还包括将与第二仓相关联的一个或多个像素渲染到第二仓，使得一个或多个像素被渲染到第一仓和第二仓。

公开(公告)号：US09489710B2

公开(公告)日：2016-11-08

申请号：US14618463

申请日：2015-02-10

Applicant: QUALCOMM Incorporated

Inventor： Tao Wang

IPC: G06T1/00 ,  G06T1/60 ,  G06T1/20 ,  G06T15/80 ,  G06T15/04

CPC classification number: G06T1/60 ,  G06F9/50 ,  G06T1/20 ,  G06T15/005 ,  G06T15/04 ,  G06T15/80 ,  G06T2200/28 ,  G06T2210/08

Abstract: This disclosure presents techniques and structures for graphics processing. In one example, a method of graphics processing may include rendering, with a graphics processing unit (GPU), one or more portions of a frame using one or more graphics operations, and writing, with the GPU, color data directly to a color buffer in a system memory in accordance with the one or more graphics operations. The method may further include writing, with the GPU, depth data to a depth buffer in a graphics memory in accordance with the one or more graphics operations, and resolving, with the GPU, the depth buffer in the graphics memory to the system memory when the rendering of the one or more portions of the frame is complete.

Abstract translation: 本公开提供用于图形处理的技术和结构。 在一个示例中，图形处理的方法可以包括使用图形处理单元（GPU），使用一个或多个图形操作来渲染帧的一个或多个部分，并且将GPU与彩色数据直接写入颜色缓冲器 在根据一个或多个图形操作的系统存储器中。 该方法还可以包括根据一个或多个图形操作将GPU深度数据写入图形存储器中的深度缓冲器，并且在GPU中将图形存储器中的深度缓冲器解析为系统存储器，当 帧的一个或多个部分的呈现完成。

公开(公告)号：US09324127B2

公开(公告)日：2016-04-26

申请号：US14454394

申请日：2014-08-07

Applicant: QUALCOMM Incorporated

Inventor： Ouns Mouri ,  Vineet Goel ,  Tao Wang

IPC: G06T1/20 ,  G06T17/10 ,  G09G5/18

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T17/10 ,  G09G5/18 ,  G09G2310/08

Abstract: This disclosure describes a method for performing conservative rasterization in a processor comprising determining vertices of a primitive, defining edges of the primitive by determining a set of edge equations based on the determined vertices, wherein the edge equations are based on an edge shifting parameter plus an offset, determining pixels that touch the edges of the primitive using the determined edge equations, and rasterizing the primitive using the determined pixels.

Abstract translation: 本公开描述了一种用于在处理器中执行保守光栅化的方法，包括通过基于所确定的顶点确定一组边缘方程来确定原语的边缘来定义基元的边缘，其中边缘方程基于边缘移位参数加上 使用所确定的边缘方程来确定触摸图元的边缘的像素，以及使用所确定的像素来对原图进行光栅化。

公开(公告)号：US20240221279A1

公开(公告)日：2024-07-04

申请号：US18609624

申请日：2024-03-19

Applicant: QUALCOMM Incorporated

Inventor： Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Dong Zhou

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a sliced low-resolution Z buffer (LRZ) that is communicatively coupled to each hardware slice of the plurality of hardware slices, and that comprises a plurality of LRZ regions. Each hardware slice is configured to store, in an LRZ region corresponding exclusively to the hardware slice among the plurality of LRZ regions, a pixel tile assigned to the hardware slice.

公开(公告)号：US12008677B2

公开(公告)日：2024-06-11

申请号：US17655358

申请日：2022-03-17

Applicant: QUALCOMM Incorporated

Inventor： Srihari Babu Alla ,  Tao Wang ,  Andrew Evan Gruber ,  Matthew Netsch ,  Richard Hammerstone ,  Thomas Edwin Frisinger

IPC: G06T1/20 ,  H04N19/182

CPC classification number: G06T1/20 ,  H04N19/182

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for compatible compression for different types of image views. A graphics processor may select a first common format of a plurality of common formats for at least one image based on at least one of application data or first metadata associated with the at least one image. The graphics processor may encode the at least one image based on the selected first common format for the at least one image. The graphics processor may select a second common format for the at least one image based on second metadata of the at least one image. The second common format may be identical to the first common format. The graphics processor may decode the at least one image based on the selected second common format for the at least one image.

公开(公告)号：US11734787B2

公开(公告)日：2023-08-22

申请号：US17478694

申请日：2021-09-17

Applicant: QUALCOMM Incorporated

Inventor： Ashokanand Neelambaran ,  Piyush Gupta ,  Kalyan Kumar Bhiravabhatla ,  Tao Wang ,  Andrew Evan Gruber

IPC: G06T1/20 ,  A63F13/525 ,  G06T3/40 ,  G06T11/40

CPC classification number: G06T1/20 ,  A63F13/525 ,  G06T3/40 ,  G06T11/40

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of primitives associated with one or more frames in a scene, a portion of the scene being associated with an upscaled sample space and/or a downscaled sample space. The apparatus may also perform a binning pass for the plurality of primitives, the binning pass being associated with an unscaled sample space, where the binning pass sorts each of the primitives into one or more bins associated with each of the one or more frames. Further, the apparatus may perform one of one or more rendering passes for each of the one or more bins. The apparatus may also rasterize each of the plurality of primitives based on at least one of the upscaled sample space or the downscaled sample space.

公开(公告)号：US11176734B1

公开(公告)日：2021-11-16

申请号：US17064188

申请日：2020-10-06

Applicant: QUALCOMM Incorporated

Inventor： Srihari Babu Alla ,  Adimulam Ramesh Babu ,  Jonnala Gadda Nagendra Kumar ,  Avinash Seetharamaiah ,  Tao Wang ,  Xuefeng Tang ,  Thomas Edwin Frisinger ,  Andrew Evan Gruber

IPC: G06T15/40 ,  G06T15/00

Abstract: The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws across a frame, each of the plurality of commands indicating a depth test direction with respect to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes maintaining, at the GPU, a LRZ status buffer to store a corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any of the plurality of commands remaining unprocessed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ status buffer.

公开(公告)号：US09959665B2

公开(公告)日：2018-05-01

申请号：US14805088

申请日：2015-07-21

Applicant: QUALCOMM Incorporated

Inventor： Nagarjuna Duvvuru ,  Tao Wang ,  Jian Liang ,  Chunlin Wang

IPC: G06T15/00 ,  G06T15/30 ,  G06T15/40 ,  G06T11/40

CPC classification number: G06T15/40 ,  G06T11/40 ,  G06T15/005 ,  G06T2200/04 ,  G06T2200/12 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.

公开(公告)号：US09311743B2

公开(公告)日：2016-04-12

申请号：US14061506

申请日：2013-10-23

Applicant: QUALCOMM Incorporated

Inventor： Tao Wang ,  Andrew Evan Gruber ,  Shambhoo Khandelwal

IPC: G06T15/40 ,  G06T15/00 ,  G06T1/60

CPC classification number: G06T15/405 ,  G06T1/60 ,  G06T15/005

Abstract: This disclosure describes techniques for performing hierarchical z-culling in a graphics processing system. In some examples, the techniques for performing hierarchical z-culling may involve selectively merging partially-covered source tiles for a tile location into a fully-covered merged source tile based on whether conservative farthest z-values for the partially-covered source tiles are nearer than a culling z-value for the tile location, and using a conservative farthest z-value associated with the fully-covered merged source tile to update the culling z-value for the tile location. In further examples, the techniques for performing hierarchical z-culling may use a cache unit that is not associated with an underlying memory to store conservative farthest z-values and coverage masks for merged source tiles. The capacity of the cache unit may be smaller than the size of cache needed to store merged source tile data for all of the tile locations in a render target.

Abstract translation: 本公开描述了在图形处理系统中执行分层z剔除的技术。 在一些示例中，用于执行分层z剔除的技术可以包括基于对于部分覆盖的源平铺的保守最远的z值是否更接近而选择性地将用于瓦片位置的部分覆盖的源瓦片合并到完全覆盖的合并源瓦片中 比用于瓦片位置的剔除z值，以及使用与完全覆盖的合并源平铺相关联的保守最远的z值来更新瓦片位置的剔除z值。 在另外的示例中，用于执行分层z剔除的技术可以使用与底层存储器不相关联的高速缓存单元来存储用于合并的源瓦片的保守最远的z值和覆盖掩码。 高速缓存单元的容量可以小于存储渲染目标中的所有瓦片位置的合并的源瓦片数据所需的高速缓存的大小。

公开(公告)号：US20150294498A1

公开(公告)日：2015-10-15

申请号：US14686696

申请日：2015-04-14

Applicant: QUALCOMM Incorporated

Inventor： Chunhui Mei ,  Tao Wang ,  Young In Yeo ,  Vineet Goel

IPC: G06T15/80 ,  G06T7/00 ,  G06T1/60 ,  G06T17/10 ,  G06T1/20

CPC classification number: G06T7/70 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T15/005 ,  G06T15/80 ,  G06T2210/12

Abstract: Techniques are described for stochastic rasterization. A graphics processing unit (GPU) may discard samples of bounding polygons that together indicate movement of one or more primitives before a pixel shader process the samples. The GPU may leverage a stencil buffer and stencil test for discarding of such samples.

Abstract translation: 技术描述为随机光栅化。 图形处理单元（GPU）可以丢弃在像素着色器处理样本之前一起指示一个或多个图元的移动的边界多边形的样本。 GPU可以利用模板缓冲区和模板测试来丢弃这样的样本。