公开(公告)号：US20150149864A1

公开(公告)日：2015-05-28

申请号：US14088867

申请日：2013-11-25

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G06F11/10

CPC classification number: G06F11/102 ,  G06F11/1064 ,  G06F12/00

Abstract: A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.

Abstract translation: 特定设备包括基于电阻的存储器件，标签随机存取存储器（RAM）和位恢复（BR）存储器。 基于电阻的存储器件被配置为存储与数据值相关联的数据值和纠错码（ECC）数据。 标签RAM被配置为存储将主存储器的存储器地址映射到高速缓冲存储器的字线的信息，其中高速缓冲存储器包括基于电阻的存储器件。 BR存储器被配置为存储与数据值相关联的附加纠错数据，其中BR存储器对应于易失性存储器设备。

公开(公告)号：US20140215294A1

公开(公告)日：2014-07-31

申请号：US13752419

申请日：2013-01-29

Applicant: QUALCOMM INCORPORATED

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim

IPC: G06F11/08

CPC classification number: G06F11/1048 ,  G11C11/16 ,  G11C17/02 ,  G11C17/146 ,  G11C17/18 ,  G11C29/027 ,  G11C2029/4402

Abstract: A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element.

Abstract translation: 电路包括第一个一次性可编程（OTP）元件和第二个OTP元件。 电路还包括耦合以从第一OTP元件接收数据的第一表示的错误检测电路。 电路还包括响应于错误检测电路的输出的输出电路，以基于数据的第一表示或基于来自第二OTP元件的数据的第二表示来输出OTP读取结果。

公开(公告)号：US20140140162A1

公开(公告)日：2014-05-22

申请号：US13680361

申请日：2012-11-19

Applicant: QUALCOMM INCORPORATED

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim

IPC: G11C8/16

CPC classification number: G11C7/20 ,  G11C16/20 ,  G11C29/44 ,  G11C29/789 ,  G11C2029/4402

Abstract: A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device.

Abstract translation: 提供了包括单元阵列和易失性存储装置的存储装置。 单元阵列可以包括多个字线，多个位线，其中字线和位线的选择定义存储器单元地址，以及用于存储单元阵列的配置信息的非易失性保留字线。 易失性存储设备耦合到单元阵列。 来自非易失性保留字线的配置信息在上电或初始化存储器件时被复制到易失性存储设备。

公开(公告)号：US20190304527A1

公开(公告)日：2019-10-03

申请号：US15939923

申请日：2018-03-29

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H04L9/32 ,  H01L43/08 ,  H01L27/22

Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.

公开(公告)号：US10319425B1

公开(公告)日：2019-06-11

申请号：US15939514

申请日：2018-03-29

Applicant: QUALCOMM Incorporated ,  Yonsei University, University-Industry Foundation

Inventor： Seong-Ook Jung ,  Byungkyu Song ,  Sungryul Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16

Abstract: Offset-cancellation sensing circuit (OCSC)-based Non-volatile (NV) memory circuits are disclosed. An OCSC-based NV memory circuit includes a latch circuit configured to latch a memory state from an input signal. The OCSC-based NV memory circuit also includes a sensing circuit that includes NV memory devices configured to store the latched memory state in the latch circuit for restoring the memory state in the latch circuit when recovering from a reduced power level in an idle mode. To avoid the need to increase transistor size in the sensing circuit to mitigate restoration degradation, the sensing circuit is also configured to cancel an offset voltage of a differential amplifier in the sensing circuit. In other exemplary aspects, the NV memory devices are included in the sensing circuit and coupled to the differential transistors as NMOS transistors in the differential amplifier, eliminating contribution of offset voltage from other differential PMOS transistors not included.

公开(公告)号：US09455014B1

公开(公告)日：2016-09-27

申请号：US14818809

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Taehyun Kim ,  Sungryul Kim ,  Seung Hyuk Kang ,  Jung Pill Kim

IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C29/44

CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C11/1659 ,  G11C11/1677 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C29/52

Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.

Abstract translation: 公开了基于写入错误率（WER）调整电阻性​​存储器写入驱动器强度的方面。 一方面，提供写入驱动器强度控制电路，以基于电阻性存储器的WER来调整提供给电阻性存储器的写入电流。 写驱动器强度控制电路包括跟踪电路，其被配置为基于对电阻性存储器元件执行的写入操作来确定电阻性存储器的WER。 写驱动器强度控制电路包括写入电流计算器电路，其被配置为将WER与表示电阻性存储器的期望产出性能水平的目标WER进行比较。 写入驱动器强度控制电路中的写入电流调整电路被配置为基于该比较来调整写入电流。 写入驱动器强度控制电路调节写入电流以执行写入操作，同时减少与击穿电压相关联的写入错误。

公开(公告)号：US09455013B2

公开(公告)日：2016-09-27

申请号：US14992753

申请日：2016-01-11

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00 ,  G11C7/14 ,  G11C11/15 ,  G11C29/02

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.

Abstract translation: 一种方法包括在电阻式存储器件中，基于第一有效参考电阻和第二有效参考电阻来确定平均有效参考电阻电平。 第一有效参考电阻基于电阻性存储器件的第一组参考单元，第二有效参考电阻基于电阻式存储器件的第二组参考单元。 该方法包括至少部分地基于平均有效参考电阻电平来修整参考电阻。 响应于确定第一有效参考电阻基本上不等于平均有效参考电阻电平，修整参考电阻包括修改与第一有效参考电阻相关联的一个或多个磁性隧道结装置的一个或多个状态。

公开(公告)号：US20160240237A1

公开(公告)日：2016-08-18

申请号：US14620487

申请日：2015-02-12

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1677 ,  G11C2013/0078

Abstract: Aspects of adjusting resistive memory write driver strength based on a mimic resistive memory write operation are disclosed. In one aspect, a write driver adjustment circuit is provided to adjust a write current provided by a write driver to a resistive memory for write operations. The write driver adjustment circuit includes a mimic write driver configured to provide a mimic write current that mimics the write current provided to the resistive memory. The mimic write current is applied to a mimic resistive memory that contains mimic resistive memory elements that mimic a resistance distribution of the resistive memory. When the mimic write current is applied, a mimic voltage is generated across the mimic resistive memory elements. The write driver adjustment circuit is configured to adjust the write current based on the mimic voltage so that the write current is sufficient for write operations, but low enough to reduce breakdown.

Abstract translation: 公开了基于模拟电阻式存储器写入操作来调节电阻性存储器写入驱动器强度的方面。 一方面，提供写入驱动器调整电路以将由写入驱动器提供的写入电流调整到用于写入操作的电阻性存储器。 写驱动器调整电路包括模拟写驱动器，其配置为提供模拟写入电流，模拟写入电流提供给电阻存储器。 模拟写入电流被施加到模拟电阻性存储器，其包含模拟电阻性存储器的电阻分布的模拟电阻存储器元件。 当应用模拟写入电流时，在模拟电阻存储器元件之间产生模拟电压。 写入驱动器调整电路被配置为基于模拟电压来调整写入电流，使得写入电流对于写入操作是足够的，但是足够低以减少击穿。

公开(公告)号：US09401226B1

公开(公告)日：2016-07-26

申请号：US14853860

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C29/00 ,  G11C11/16 ,  G11C29/44

CPC classification number: G11C29/76 ,  G06F12/0238 ,  G06F2212/7207 ,  G06F2212/7209 ,  G11C7/20 ,  G11C11/1653 ,  G11C29/44 ,  G11C29/789 ,  G11C29/808 ,  G11C29/82 ,  G11C29/84

Abstract: A device includes a redundant region of a magnetoresistive random access memory (MRAM) array that includes first memory cells. The device includes a data region of the MRAM array that includes second memory cells. The device includes a fail address region of the MRAM array, a first row of the fail address region including validity data, wherein the validity data includes multiple validity indicators, a last row indicator, or both.

Abstract translation: 一种器件包括包含第一存储器单元的磁阻随机存取存储器（MRAM）阵列的冗余区域。 该装置包括包括第二存储器单元的MRAM阵列的数据区域。 该装置包括MRAM阵列的故障地址区域，包括有效性数据的故障地址区域的第一行，其中有效性数据包括多个有效性指示符，最后一行指示符或两者。

公开(公告)号：US09336847B2

公开(公告)日：2016-05-10

申请号：US14257794

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Taehyun Kim ,  Jung Pill Kim

IPC: G11C7/14 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/1659

Abstract: Methods and apparatus for generating a reference for use with a magnetic tunnel junction are provided. In an example, provided is a magnetoresistive read only memory including a magnetic tunnel junction (MTJ) storage element, a sense amplifier having a first input coupled to the MTJ storage element, and a reference resistance device coupled to a second input of the sense amplifier. The reference resistance device includes a plurality of groups of at least two reference MTJ devices. Each reference MTJ device in a respective group is coupled in parallel with each other reference MTJ device in the respective group. Each group is coupled in series with the other groups. This arrangement advantageously mitigates read disturbances and reference level variations, while saving power, reducing reference resistance device area, and increasing read speed.

Abstract translation: 提供了用于产生用于磁性隧道结的参考的方法和装置。 在一个例子中，提供了一种包括磁性隧道结（MTJ）存储元件的磁阻只读存储器，具有耦合到MTJ存储元件的第一输入的读出放大器和耦合到读出放大器的第二输入的参考电阻器件 。 参考电阻装置包括多组至少两个参考MTJ装置。 相应组中的每个参考MTJ设备与相应组中的每个其他参考MTJ设备并联耦合。 每个组与其他组串联。 这种布置有利于减轻读取干扰和参考电平变化，同时节省功率，减少参考电阻器件面积并增加读取速度。