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Patent Agency Ranking
公开(公告)号：US10491173B2
公开(公告)日：2019-11-26
申请号：US15940808
申请日：2018-03-29
Applicant: Qualcomm Incorporated
Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.
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公开(公告)号：US10340860B1
公开(公告)日：2019-07-02
申请号：US16138765
申请日：2018-09-21
Applicant: QUALCOMM INCORPORATED
Inventor： Chuan Wang , Wei Cheng , Kevin Hsi Huai Wang
Abstract: A circuit includes a passive low gain low noise amplifier (LNA) configured to receive a communication signal, an active low gain LNA configured to receive the communication signal, a shared coupling circuit, outputs of the passive low gain LNA and the active low gain LNA coupled to the shared coupling circuit, an output circuit, an output of the shared coupling circuit coupled to the output circuit, and a high gain LNA configured to receive the communication signal, the high gain LNA coupled to the output circuit along a path that bypasses the shared coupling circuit.
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公开(公告)号：US20190158042A1
公开(公告)日：2019-05-23
申请号：US15940808
申请日：2018-03-29
Applicant: Qualcomm Incorporated
IPC: H03F1/56 , H03H7/38 , H03F1/22 , H04B1/3827
Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.
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公开(公告)号：US09154088B2
公开(公告)日：2015-10-06
申请号：US14105126
申请日：2013-12-12
Applicant: QUALCOMM Incorporated
Inventor： Yang Xu , Timothy Paul Pals , Kevin Hsi Huai Wang
CPC classification number: H03F3/04 , G01S19/21 , G01S19/34 , G01S19/36 , H03F1/02 , H03F1/223 , H03F1/3205 , H03F3/19 , H03F3/24 , H04B7/18513 , H04B2001/045 , Y02D70/1222 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/446
Abstract: A method of selecting a mode for an SPS receiver includes selecting either a first mode or a second mode for the SPS receiver based on a comparison between an output power of a communications transceiver and a mode switch point wherein the mode switch point is a power value. The first mode corresponds to a first bias current value of the SPS receiver, the second mode corresponds to a second bias current value of the SPS receiver, and the first bias current value is different from the second bias current value.
Abstract translation: 选择SPS接收机的模式的方法包括：基于通信收发器的输出功率与模式切换点之间的比较来选择用于SPS接收机的第一模式或第二模式，其中模式切换点是功率值 。 第一模式对应于SPS接收机的第一偏置电流值，第二模式对应于SPS接收机的第二偏置电流值，并且第一偏置电流值不同于第二偏置电流值。
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公开(公告)号：US20140162570A1
公开(公告)日：2014-06-12
申请号：US13712607
申请日：2012-12-12
Applicant: QUALCOMM INCORPORATED
Inventor： I-Hsiang Lin , Zhijie Xiong , Seshagiri Krishnamoorthy , Jin-Su Ko , Prashanth Akula , Liang Zhao , Kevin Hsi Huai Wang , Desong Zhao
IPC: H04B1/38
CPC classification number: H04B1/0064
Abstract: An RFIC configuration for reduced antenna trace loss is disclosed. In an exemplary embodiment, an apparatus includes a primary RFIC and a secondary RFIC that is configured to receive analog signals from at least two antennas. The secondary RFIC is configured to process selected analog signals received from at least one antenna to generate an analog output that is input to the primary RFIC.
Abstract translation: 公开了一种用于降低天线轨迹损耗的RFIC配置。 在示例性实施例中，装置包括主RFIC和辅助RFIC，其被配置为从至少两个天线接收模拟信号。 辅助RFIC被配置为处理从至少一个天线接收的所选模拟信号，以产生输入到主RFIC的模拟输出。
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