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    INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING ADDED METAL FOR EMBEDDED METAL TRACES IN ETS-BASED SUBSTRATE FOR REDUCED SIGNAL PATH IMPEDANCE, AND RELATED FABRICATION METHODS
    24.
    发明申请
    INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING ADDED METAL FOR EMBEDDED METAL TRACES IN ETS-BASED SUBSTRATE FOR REDUCED SIGNAL PATH IMPEDANCE, AND RELATED FABRICATION METHODS 有权

    公开(公告)号：US20230086094A1

    公开(公告)日：2023-03-23

    申请号：US17482718

    申请日：2021-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

    IPC: H01L23/498 ,  H01L21/48

    Abstract: Integrated circuit (IC) packages employing added metal for embedded metal traces in an ETS-based substrate for reduced signal path impedance. An IC package includes a package substrate and an ETS metallization layer disposed on the package substrate. To mitigate or offset an increase in impedance in longer signal paths between die circuitry and the package substrate that can result in decreased signaling speed and/or increased signal loss, added metal interconnects are coupled to embedded metal traces in the ETS metallization layer. Thus, embedded metal traces of the ETS metallization layer coupled to signal/ground signal paths of the die are increased in metal surface area. Increasing metal surface area of embedded metal traces coupled to the signal/ground signal paths of a die increases capacitance of such signal/ground signal paths. Increasing capacitance of signal/ground signal paths decreases impedance of the signal/ground signal paths to mitigate or reduce signaling delay and/or loss.

    Substrate comprising a high-density interconnect portion embedded in a core layer
    26.
    发明授权
    Substrate comprising a high-density interconnect portion embedded in a core layer 有权

    公开(公告)号：US11552015B2

    公开(公告)日：2023-01-10

    申请号：US16900672

    申请日：2020-06-12

    Applicant: QUALCOMM Incorporated

    Inventor： Aniket Patil ,  Hong Bok We ,  Kuiwon Kang

    IPC: H01L23/528 ,  H01L23/00 ,  H01L27/146 ,  H01L39/24 ,  H01L21/768

    Abstract: A substrate that includes a core layer comprising a first surface and a second surface, a plurality of core interconnects located in the core layer, a high-density interconnect portion located in the core layer, a first dielectric layer coupled to the first surface of the core layer, a first plurality of interconnects located in the first dielectric layer, a second dielectric layer coupled to the second surface of the core layer, and a second plurality of interconnects located in the second dielectric layer. The high-density interconnect portion includes a first redistribution dielectric layer and a first plurality of high-density interconnects located in the first redistribution dielectric layer. The high-density interconnect portion may provide high-density interconnects.

    X.5 layer substrate
    28.
    发明授权
    X.5 layer substrate 有权

    公开(公告)号：US11183446B1

    公开(公告)日：2021-11-23

    申请号：US16994910

    申请日：2020-08-17

    Applicant: QUALCOMM Incorporated

    Inventor： Jaehyun Yeon ,  Suhyung Hwang ,  Hong Bok We ,  Kun Fang

    IPC: H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K3/40 ,  H05K3/10

    Abstract: X.5 layer substrates that do not use an embedded traces substrate process during formation may produce a high yield with relaxed L/S in a short manufacturing time (only 4× lamination process without a detach process) at a low cost. For example, a substrate may include an mSAP, two landing pads, two escape lines, two bump pads, and a photo-imageable dielectric layer on the mSAP patterned substrate.

    Through-package partial via on package edge
    29.
    发明授权
    Through-package partial via on package edge 有权

    公开(公告)号：US11101220B2

    公开(公告)日：2021-08-24

    申请号：US16553283

    申请日：2019-08-28

    Applicant: QUALCOMM Incorporated

    Inventor： Hong Bok We ,  Aniket Patil ,  Jaehyun Yeon

    IPC: H01L23/48 ,  H01L23/538 ,  H01L23/498 ,  H01L21/50 ,  H01L21/768 ,  H01L21/60

    Abstract: Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.

    Array type inductor
    30.
    发明授权
    Array type inductor 有权

    公开(公告)号：US10403707B2

    公开(公告)日：2019-09-03

    申请号：US15476823

    申请日：2017-03-31

    Applicant: QUALCOMM Incorporated

    Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Joonsuk Park

    IPC: H01F17/00 ,  H01L49/02 ,  H01F17/04 ,  H01F27/29

    Abstract: Examples of this disclosure include a low profile inductor for use in any application with a multi-layer inductor pattern that allows control of optimum H values. Some examples of such an inductive device comprises a plurality of patterned metal coils arranged in a vertical stack, a plurality of conductive vias configured to couple each of the plurality of patterned metal coils together, and a magnetic material disposed between the plurality of patterned metal coils and within each of the plurality of patterned metal coils.

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