Abstract:
An output circuit of a driver includes a plurality of output nodes, a first output buffer group and a multiplexer. The first output buffer group is configured to output data to the plurality of output nodes, wherein each output buffer in the first output buffer group is configured to output data to at least two output nodes among the plurality of output nodes. The multiplexer, coupled between the plurality of output nodes and the first output buffer group, is configured to select to couple each output buffer in the first output buffer group to one of the plurality of output nodes.
Abstract:
The invention provides a display panel driving apparatus and a driving method thereof. The display panel driving apparatus includes a source driver circuit and a timing controller circuit. The source driver circuit loads data to data lines of the display panel in load data periods. The timing controller circuit controls the source driver circuit for dynamically configuring a time length of one of the load data periods according to whether charge sharing occurs. When a charge sharing operation is not performed on at least two of the data lines in the load data period, the load data period has a first time length. When the charge sharing operation is performed on at least two of the data lines in the load data period, the load data period has a second time length longer than the first time length.
Abstract:
A timing controller and an operation method thereof are provided. The timing controller includes a transmitter circuit and a control circuit. The control circuit ends a normal mode and enter a swing boost mode when quality of data signal is detected to be deteriorated in the normal mode. In the swing boost mode, the control circuit boosts the swing of the data signal to be higher than a normal level of the data signal in the normal mode.
Abstract:
A driving circuit and an anti-interference method thereof are provided. The driving circuit includes a source driver. The source driver is configured to be controlled by a timing controller. The source driver is configured to adjust at least one of an operation frequency and a receiving bandwidth of a source driving circuit of the source driver when at least one of the timing controller and the source driver detects that an interference event occurs.
Abstract:
A timing controller and an anti-interference method thereof are provided. The timing controller includes a timing control circuit. The timing control circuit provides an input signal for controlling a source driver. When at least one of the timing control circuit and the source driver detects that an interference event occurs to the input signal, the timing control circuit is configured to adjust a frequency of a data signal or a clock signal from a normal operation frequency to at least one anti-interference frequency. The timing control signal is further configured to provide at least one of the data signal and the clock signal to the source driver.
Abstract:
A method of controlling image data includes the steps of: detecting a frame of image data to determine an image pattern of the frame of image data; and determining to output the frame of image data with one of a plurality of configurations according to the image pattern. Wherein, a first configuration among the plurality of configurations indicates that the frame of image data is outputted in a first sequence and a second configuration among the plurality of configurations indicates that the frame of image data is outputted in a second sequence different from the first sequence.
Abstract:
A method of handling operation of a source driver of a display system used in a timing controller of a display system, which is coupled to the source driver via a data bus for delivering a plurality of line data, includes determining whether a first line data among the plurality of line data is identical to a second line data among the plurality of line data previous to the first line data; and transmitting a sleep command to the source driver when the first line data is determined to be identical to the second line data, wherein the sleep command instructs the source driver to enter a sleep mode; wherein the source driver stops receiving the plurality of line data from the timing controller when the source driver is in the sleep mode.
Abstract:
A method of controlling data display on a panel includes displaying a first row data by turning on a first scan line; comparing a plurality of row data with the first row data, to generate a comparison result; determining an order of displaying the plurality of row data according to the comparison result; and outputting the plurality of row data and turning on a plurality of scan lines corresponding to the plurality of row data in the order, to display the plurality of row data in the order.
Abstract:
A display apparatus includes a source driver and a display panel. The source driver provides a plurality of pixel voltages which respectively correspond to a maximum gray-level voltage or a minimum gray-level voltage. The display panel includes a plurality of data lines, a plurality of pixel switches, a plurality of pixel capacitors, and a plurality of gray-level switches. The data lines are coupled to the source driver to receive the pixel voltages. Each pixel switch is respectively coupled to the corresponding data line to transmit the corresponding pixel voltage. Each pixel capacitor is respectively coupled between the corresponding pixel switch and a common voltage to receive the corresponding pixel voltage. Each gray-level switch is respectively coupled to the corresponding pixel capacitor in parallel and respectively receives a gray-level control signal. The gray-level switches regulate voltage drops across the pixel capacitors according to the corresponding gray-level control signals.
Abstract:
A display driving apparatus with a power control circuit reducing power consumption includes: a shift register receiving a display data signal and outputting a plurality of data signals; a first latch receiving a Nth data signal of the plurality of data signals and outputting a first latched data signal according to a first gate driving signal; an analog signal processing circuit including a second latch coupling to the first latch and outputting a second latched data signal according to a second gate driving signal; a data comparator comparing the first latched data signal and the second latched data signal; and a power controller coupling to the data comparator and controlling a power level of the analog signal processing circuit.