公开(公告)号：US09614536B2

公开(公告)日：2017-04-04

申请号：US15080222

申请日：2016-03-24

Applicant: NXP B.V.

Inventor： Ulrich Moehlmann

IPC: H03L7/06 ,  H03L7/095 ,  H03L7/093 ,  H03L7/099

CPC classification number: H03L7/095 ,  H03L7/093 ,  H03L7/0991 ,  H03L2207/50

Abstract: A phase locked loop is disclosed comprising: a phase detector, loop filter and a frequency controlled oscillator. The phase detector is configured to determine a phase difference between a reference signal and a feedback signal. The loop filter is configured to perform a filtering operation on a signal derived from the phase difference and to provide a control signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The phase locked loop further comprises a lock detector, including: a phase lock detector configured to receive a first signal from the phase locked loop, and to derive a phase lock signal from the first signal; a frequency lock detector configured to receive a second signal from the phase locked loop, and to derive a frequency lock signal from the second signal. An unlock detector may be provided, configured to determine whether the first signal has changed by a predetermined amount during a predetermined period.