Abstract:
A modulation circuit includes a phase locked loop (PLL) circuit, a scalar circuit and a sigma-delta modulator. The PLL circuit is for generating an output oscillating signal in response to a reference signal, a first control signal and a second control signal. The scalar circuit is for generating the first control signal in response to modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form. The sigma-delta modulator is for generating the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit.
Abstract:
A communication device with a power detection scheme is disclosed. The communication device includes a transmitter for transmitting an RF signal, a demodulator for demodulating the RF signal by utilizing a phase-modulated (PM) signal provided from the transmitter to generate a demodulated signal, a loopback circuit coupled between the transmitter and the demodulator for transmitting the RF signal and the PM signal from the transmitter to the demodulator when the power detection scheme is enabled, and a power detector for detecting power of the demodulated signal.
Abstract:
A data converting device includes: a data sampling circuit arranged to up-sample a digital signal to generate an up-sampling signal according to a clock signal; a voltage level generating circuit arranged to generate an adjustable voltage; and a signal converting circuit arranged to generate a converting signal according to the adjustable voltage and the up-sampling signal.
Abstract:
A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.
Abstract:
A method for implicitly signaling a transmit (Tx) switching configuration includes: configuring a first signaling message to indicate a band combination of a plurality of bands; and sending the first signaling message, wherein the Tx switching configuration is implicitly signaled by an order of the plurality of bands of the band combination indicated by the first signaling message.
Abstract:
A method operative on a wireless transceiver device for performing beamforming calibration includes: measuring at least one joint signal response of at least one circuit loopback between a transmitter of the wireless transceiver device and a receiver of the wireless transceiver device to determine the measurement result; and calibrating joint signal path mismatch according to the measurement result for s multiple antenna beamforming system operating on the wireless transceiver device.
Abstract:
A transmitter device with I/Q mismatch compensation and a method thereof are provided. The transmitter device includes a transmitter circuit, a loop-back circuit and a baseband circuit. The transmitter circuit is configured to convert a baseband signal into an RF signal based on a specific gain configuration of a plurality of gain configurations. The loop-back circuit is configured to retrieve the RF signal from the transmitter circuit. The baseband circuit is configured to compensate the baseband signal by specific transmitter I/Q mismatch corresponding to the specific gain configuration, wherein a plurality of transmitter IQ mismatches are determined for the plurality of gain configurations by the retrieved RF signal, and the specific transmitter I/Q mismatch among the plurality of transmitter IQ mismatches is determined by the retrieved RF signal, which is converted in response to the specific gain configuration, from the loop-back circuit.
Abstract:
A signal transmitting device includes: a signal processing circuit arranged to process an input signal to generate a processed input signal according to a compensating signal; a signal converting circuit arranged to convert the processed input signal to generate an output signal according to an oscillating signal; and an arithmetic circuit arranged to generate the compensating signal according to the power of a predetermined component in the output signal, wherein the signal processing circuit uses the compensating signal to update the input signal, and the signal converting circuit converts the updated input signal to reduce the power of the predetermined component in the output signal.