-
公开(公告)号：US10432227B2
公开(公告)日：2019-10-01
申请号：US15878350
申请日：2018-01-23
Applicant: MediaTek Inc.
Inventor： Wei-Jen Chen , Ju-Ya Chen , Yen-Shuo Chang , Timothy Perrin Fisher-Jeffes , Mao-Ching Chiu , Cheng-Yi Hsu , Chong-You Lee
Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.
-
Patent Agency Ranking
公开(公告)号：US20190097657A1
公开(公告)日：2019-03-28
申请号：US16199216
申请日：2018-11-25
Applicant: MediaTek Inc.
Inventor： Mao-Ching Chiu , Chong-You Lee , Cheng-Yi Hsu , Timothy Perrin Fisher-Jeffes , Yen-Shuo Chang , Wei-Jen Chen , Ju-Ya Chen
CPC classification number: H03M13/1168 , H03M13/033 , H03M13/116 , H03M13/616 , H03M13/6306 , H03M13/6516 , H04L1/0057 , H04L1/0068 , H04L1/1819
Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value
-
23.发明申请公开(公告)号：US20180331695A1
公开(公告)日：2018-11-15
申请号：US16021015
申请日：2018-06-28
Applicant: MediaTek Inc.
Inventor： Timothy Perrin Fisher-Jeffes , Chong-You Lee , Mao-Ching Chiu , Wei-Jen Chen , Ju-Ya Chen
IPC: H03M13/11
CPC classification number: H03M13/116 , H03M13/036 , H03M13/1145 , H03M13/6306 , H03M13/6516
Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.
-
公开(公告)号：US20180227077A1
公开(公告)日：2018-08-09
申请号：US15888733
申请日：2018-02-05
Applicant: MEDIATEK INC.
Inventor： Chong-You LEE , Cheng-Yi Hsu , Maoching Chiu , Timothy Perrin Fisher-Jeffes , Ju-Ya Chen , Yen Shuo Chang , Wei Jen Chen
Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.
-
公开(公告)号：US20180212628A1
公开(公告)日：2018-07-26
申请号：US15878357
申请日：2018-01-23
Applicant: MediaTek Inc.
Inventor： Ju-Ya Chen , Cheng-Yi Hsu , Yen-Shuo Chang , Wei-Jen Chen , Mao-Ching Chiu , Timothy Perrin Fisher-Jeffes , Chong-You Lee
CPC classification number: H03M13/2792 , H03M13/1105 , H03M13/116 , H03M13/255 , H03M13/2707 , H04L1/0041 , H04L1/0058 , H04L1/0071
Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.
-
公开(公告)号：US20180205505A1
公开(公告)日：2018-07-19
申请号：US15874830
申请日：2018-01-18
Applicant: MediaTek Inc.
Inventor： Timothy Perrin Fisher-Jeffes
CPC classification number: H04L1/1816 , H04L1/005 , H04L1/0071 , H04L1/1819 , H04L1/1845
Abstract: Examples pertaining to high code-rate iterative codes combined with HARQ are provided. Proposed architectures of the present disclosure take advantage of the incremental redundancy transmitted to a receiver beyond the limits of what the HARQ can store. In the proposed architectures, internally decoded intrinsic information or extrinsic information are retained that would otherwise be discarded from the final iteration. This is then used in combination with any further new re-transmissions that may be received.
-
-
-
-
-
Search Results
26
records
(took 0.041 seconds)
