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公开(公告)号：US11257866B2
公开(公告)日：2022-02-22
申请号：US16692586
申请日：2019-11-22
摘要： A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.
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公开(公告)号：US10833123B2
公开(公告)日：2020-11-10
申请号：US16248010
申请日：2019-01-15
摘要： A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.
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公开(公告)号：US10763374B2
公开(公告)日：2020-09-01
申请号：US16414406
申请日：2019-05-16
IPC分类号： H01L29/872 , H01L21/02 , H01L27/24 , H01L21/20 , H01L45/00 , H01L29/66 , H01L29/868 , H01L29/861
摘要： A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.
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公开(公告)号：US10566531B2
公开(公告)日：2020-02-18
申请号：US15816751
申请日：2017-11-17
发明人： Matthew J. BrightSky
摘要： An illustrative method of fabricating a memory array structure includes: forming at least one access device layer on an upper surface of a first conductive layer, the access device layer being in electrical connection with the first conductive layer; forming a sacrificial layer on an upper surface of the access device layer; etching the access device layer and the sacrificial layer using a same masking feature to form an access device that is self-aligned with a portion of the sacrificial layer; replacing a portion of the sacrificial layer with memory storage material to form a storage element, a first terminal of the storage element being in electrical connection with the access device; and forming a second conductive layer on an upper surface of the storage element, a second terminal of the storage element being in electrical connection with the second conductive layer.
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25.发明申请公开(公告)号：US20190305142A1
公开(公告)日：2019-10-03
申请号：US16414406
申请日：2019-05-16
IPC分类号： H01L29/872 , H01L21/02 , H01L27/24 , H01L21/20
摘要： A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.
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公开(公告)号：US10374103B1
公开(公告)日：2019-08-06
申请号：US15938705
申请日：2018-03-28
IPC分类号： H01L21/338 , H01L29/872 , H01L21/02 , H01L27/24 , H01L21/20
摘要： A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.
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公开(公告)号：US20190157556A1
公开(公告)日：2019-05-23
申请号：US15816751
申请日：2017-11-17
发明人： Matthew J. BrightSky
摘要： An illustrative method of fabricating a memory array structure includes: forming at least one access device layer on an upper surface of a first conductive layer, the access device layer being in electrical connection with the first conductive layer; forming a sacrificial layer on an upper surface of the access device layer; etching the access device layer and the sacrificial layer using a same masking feature to form an access device that is self-aligned with a portion of the sacrificial layer; replacing a portion of the sacrificial layer with memory storage material to form a storage element, a first terminal of the storage element being in electrical connection with the access device; and forming a second conductive layer on an upper surface of the storage element, a second terminal of the storage element being in electrical connection with the second conductive layer.
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公开(公告)号：US10256271B1
公开(公告)日：2019-04-09
申请号：US15827238
申请日：2017-11-30
摘要： A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.
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公开(公告)号：US10141503B1
公开(公告)日：2018-11-27
申请号：US15803349
申请日：2017-11-03
IPC分类号： H01L45/00
摘要： A metal liner is deposited conformally to a pore within a first dielectric material of a semiconductor device. The pore extends through the first dielectric material to a top surface of a first metal electrode. The metal liner is etched such that the metal liner only substantially remains on sidewalls of the pore. A phase change material is selectively deposited within the pore of the first dielectric layer to substantially fill the pore with the phase change material. The selective deposition of the phase change material produces a growth rate of phase change material on the metal liner at a substantially greater rate than a growth rate of the phase change material on exposed surfaces of the first dielectric material.
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公开(公告)号：US09263336B2
公开(公告)日：2016-02-16
申请号：US14288600
申请日：2014-05-28
发明人： Matthew J. BrightSky , Jin Cai , SangBum Kim , Chung H. Lam , Tak H. Ning
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/24 , H01L27/22
CPC分类号： H01L21/8222 , H01L27/1022 , H01L27/226 , H01L27/2445 , H01L29/66234
摘要： A method of manufacturing a bipolar junction transistor (BJT) array may include forming a substrate of doped silicon and forming a plurality of BJTs on the substrate. Each of the BJTs may have a first region and a second region sandwiching a base region vertically. The first region may be in contact with the substrate, where the BJTs are formed in a first row and a second row. The first row and the second row may each have BJTs separated from one another by a word line distance and the first row and second row may be separated by a bit line distance. A plurality of word line contacts may be formed laterally enclosing and electrically connected to each base region of the BJTs. The word line contacts may have a lateral thickness more than one half the word line distance and less than one half the bit line distance.
摘要翻译： 制造双极结型晶体管（BJT）阵列的方法可以包括形成掺杂硅的衬底并在衬底上形成多个BJT。 每个BJT可以具有第一区域和第二区域，垂直地夹着基底区域。 第一区域可以与基底接触，其中BJT形成在第一行和第二行中。 第一行和第二行可以各自具有通过字线距离彼此分开的BJT，并且第一行和第二行可以被位线距离分隔。 多个字线触点可以横向包围并电连接到BJT的每个基区。 字线触点可以具有大于字线距离的一半的横向厚度，并且小于位线距离的一半。
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