公开(公告)号：US20180060247A1

公开(公告)日：2018-03-01

申请号：US15620663

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/02 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09678890B2

公开(公告)日：2017-06-13

申请号：US14867025

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/02 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1045

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US20170052832A1

公开(公告)日：2017-02-23

申请号：US15226864

申请日：2016-08-02

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Dion Rodgers ,  Richard A. Uhlig ,  Lawrence O. Smith ,  Barry E. Huntley

IPC: G06F9/54 ,  G06F9/48 ,  G06F9/455

CPC classification number: G06F9/45533 ,  G06F9/3861 ,  G06F9/45545 ,  G06F9/4555 ,  G06F9/45558 ,  G06F9/4812 ,  G06F9/542 ,  G06F13/24 ,  G06F2009/45566

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a hardware processor including event circuit to recognize a virtualization event, and evaluation circuit to determine whether to transfer control of the apparatus from a child guest to a parent guest in response to the virtualization event, wherein the child guest and the parent guest each include a bit per virtualization event to indicate whether the parent guest is to gain control when the virtualization event occurs.

Abstract translation: 公开了在分层虚拟化架构中处理虚拟化事件的装置和方法的实施例。 在一个实施例中，一种装置包括硬件处理器，包括用于识别虚拟化事件的事件电路，以及评估电路，用于响应虚拟化事件确定是否将该设备的控制从子客户转移到父访客，其中，该子客户机 并且父客户每个包含一个虚拟化事件，以指示在虚拟化事件发生时父访客是否获得控制。

公开(公告)号：US20160019165A1

公开(公告)日：2016-01-21

申请号：US14867024

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/08

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09164920B2

公开(公告)日：2015-10-20

申请号：US14569069

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard UhligQ ,  Lawrence Smith, III ,  Scott D. Rodgers

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/14

CPC classification number: G06F12/1483 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/657

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract translation: 一种处理器，其包括具有存储器虚拟化支持系统的处理器的虚拟化系统，以将参考映射到由虚拟机上可执行的客户机软件制成的客体物理存储器，该虚拟机器又可在主机上执行，其中处理器可操作为 引用主机的主机物理内存。

公开(公告)号：US09122624B2

公开(公告)日：2015-09-01

申请号：US14517849

申请日：2014-10-18

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract translation: 一种处理器，包括执行指令以使来自基于虚拟化的系统的客户机的物理地址（客户物理地址）到基于虚拟化系统的主机的物理地址（主机物理地址）的映射同步的指令，并且存储在 翻译后备缓冲器（TLB），其中相应的映射存储在基于虚拟化的系统的扩展分页表（EPT）中。

公开(公告)号：US20150205736A1

公开(公告)日：2015-07-23

申请号：US14565718

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard A. Uhlig ,  Udo Steinberg ,  Sebastian Schoenberg ,  Sridhar Muthrasanallur ,  Steven M. Bennett ,  Andrew V. Anderson ,  Erik C. Cota-Robles

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract translation: 公开了用于向虚拟处理器递送中断的装置，方法和系统的实施例。 在一个实施例中，装置包括用于接收中断请求，传递逻辑和退出逻辑的接口。 交付逻辑是基于中断请求的属性来确定中断请求是否被传送到虚拟处理器。 如果传递逻辑确定中断请求不被传送到虚拟处理器，则出口逻辑是将控制传送到主机。

公开(公告)号：US08997099B2

公开(公告)日：2015-03-31

申请号：US13837737

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Dion Rodgers ,  Richard A. Uhlig ,  Lawrence O. Smith ,  Barry E. Huntley

IPC: G06F9/455 ,  G06F13/00 ,  G06F9/44 ,  G06F13/24 ,  G06F13/12 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/45533 ,  G06F9/3861 ,  G06F9/45545 ,  G06F9/4555 ,  G06F9/45558 ,  G06F9/4812 ,  G06F9/542 ,  G06F13/24 ,  G06F2009/45566

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract translation: 公开了在分层虚拟化架构中处理虚拟化事件的装置和方法的实施例。 在一个实施例中，装置包括事件逻辑和评估逻辑。 事件逻辑是识别虚拟化事件。 评估逻辑是为了响应于虚拟化事件来确定是否将控制从子客户端传送到父访客。

公开(公告)号：US10180911B2

公开(公告)日：2019-01-15

申请号：US15620663

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/0875 ,  G06F12/1045 ,  G06F9/455 ,  G06F12/02 ,  G06F12/1036 ,  G06F12/1009

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09442868B2

公开(公告)日：2016-09-13

申请号：US14565718

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard A. Uhlig ,  Udo Steinberg ,  Sebastian Schoenberg ,  Sridhar Muthrasanallur ,  Steven M. Bennett ,  Andrew V. Anderson ,  Erik C. Cota-Robles

IPC: G06F9/445 ,  G06F9/46 ,  G06F13/24 ,  G06F13/26 ,  G06F3/00 ,  G06F13/00 ,  G06F9/455 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.