公开(公告)号：US20240096871A1

公开(公告)日：2024-03-21

申请号：US17947524

申请日：2022-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Terence Hook ,  Junli Wang ,  Miaomiao Wang

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0292

Abstract: An integrated circuit is presented including a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, the DUT being electrically connected to the protection diode by either at least one gate contact or at least on CA contact or at least one buried power rail (BPR). The protection diode is electrically connected to the DUT by middle-of-line (MOL) layers for gate oxide protection before M1 formation.

公开(公告)号：US11663391B2

公开(公告)日：2023-05-30

申请号：US17411113

申请日：2021-08-25

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Ryan Michael Kruse ,  Leon Sigal ,  Richard Edward Serton ,  Matthew Stephen Angyal ,  Terence Hook ,  Richard Andre Wachnik

IPC: G06F30/394 ,  H01L27/02

CPC classification number: G06F30/394 ,  H01L27/0207

Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

公开(公告)号：US11245020B2

公开(公告)日：2022-02-08

申请号：US16745100

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/786

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US12230629B2

公开(公告)日：2025-02-18

申请号：US17703092

申请日：2022-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence Hook

IPC: H01L27/085 ,  H01L27/02 ,  H01L27/092

Abstract: A set of transistor elements includes a substrate of a first doping type and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell. The set of transistor element also includes an anti-propagation region of the first doping type between the first well and the second well.

公开(公告)号：US20240413164A1

公开(公告)日：2024-12-12

申请号：US18331965

申请日：2023-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Lawrence A. Clevenger ,  Kisik Choi ,  Terence Hook

IPC: H01L27/12 ,  H01L21/84

Abstract: A microelectronic structure including a logic device and a passive device. The passive device includes a doped substrate, a silicide layer located on a backside surface of the doped substrate, and a metal plane located on a backside surface of the silicide layer.

公开(公告)号：US20240405112A1

公开(公告)日：2024-12-05

申请号：US18327114

申请日：2023-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Kisik Choi ,  Terence Hook ,  Alexander Reznicek ,  Daniel Schmidt ,  Tsung-Sheng Kang

IPC: H01L29/775 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.

公开(公告)号：US12040250B2

公开(公告)日：2024-07-16

申请号：US17841202

申请日：2022-06-15

Applicant: International Business Machines Corporation

Inventor： Terence Hook ,  Brent A. Anderson ,  Anthony I. Chou

IPC: H01L23/427 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L23/427 ,  H01L23/5226 ,  H01L27/1203

Abstract: A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs. The heat pipe includes at least one vertical interconnect structure that continuously extends between each tier of the vertically stacked FETs.

公开(公告)号：US12015069B2

公开(公告)日：2024-06-18

申请号：US16745049

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US20240096948A1

公开(公告)日：2024-03-21

申请号：US17945275

申请日：2022-09-15

Applicant: International Business Machines Corporation

Inventor： Terence Hook

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor structures such as, for example, stacked nanosheet devices, having enhanced gate resistance are provided. The enhanced gate resistance is obtained by providing a shunting material pillar in the structure and along a sidewall (or opposing sidewalls) of at least one gate structure. The shunting material pillar has a resistivity that is lower than a resistivity of the gate structure that it is laterally adjacent to.

公开(公告)号：US20230317722A1

公开(公告)日：2023-10-05

申请号：US17703092

申请日：2022-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence Hook

IPC: H01L27/085

CPC classification number: H01L27/085

Abstract: A set of transistor elements includes a substrate of a first doping type and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell. The set of transistor element also includes an anti-propagation region of the first doping type between the first well and the second well