公开(公告)号：US10014297B1

公开(公告)日：2018-07-03

申请号：US15589312

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Wenhui Wang ,  Xunyuan Zhang ,  Ruilong Xie ,  Jia Zeng ,  Xuelian Zhu ,  Min Gyu Sung ,  Shao Beng Law

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/6681

Abstract: One aspect of the disclosure is directed to a method of forming an integrated circuit structure. The method may include: providing a set of fins over a semiconductor substrate, the set of fins including a plurality of working fins and a plurality of dummy fins, the plurality of dummy fins including a first subset of dummy fins within a pre-defined distance from any of the plurality of working fins, and a second subset of dummy fins beyond the pre-defined distance from any of the plurality of working fins; removing the first subset of dummy fins by an extreme ultraviolet (EUV) lithography technique; and removing at least a portion of the second subset of dummy fins.

公开(公告)号：US20150023583A1

公开(公告)日：2015-01-22

申请号：US13943253

申请日：2013-07-16

Applicant: Globalfoundries, Inc.

Inventor： Lei Sun ,  Obert Reeves Wood, III

IPC: G01T1/02 ,  G06T7/00 ,  G01J1/42

CPC classification number: G06T7/0004 ,  G06T2207/10061 ,  G06T2207/20056 ,  G06T2207/30148

Abstract: A method of determining a dose-to-clear of a photoresist on a wafer includes providing an image of the wafer after the photoresist was exposed to a dose of energy and was developed, transforming the image of the wafer into frequency spectrum data, calculating an average frequency spectrum component of the frequency spectrum data, calculating a difference between the average frequency spectrum component and a noise average frequency spectrum component of a noise average frequency spectrum, and determining a dose-to-clear of the photoresist based on the difference between the average frequency spectrum component and the noise average frequency spectrum component.

Abstract translation: 确定晶片上的光致抗蚀剂的剂量清除的方法包括在光致抗蚀剂暴露于一定量的能量之后提供晶片的图像，并将其显影，将晶片的图像转换成频谱数据，计算 计算频谱数据的平均频谱分量，计算噪声平均频谱的平均频谱分量和噪声平均频谱分量之间的差，并且基于所述光谱的差异来确定光致抗蚀剂的剂量 - 平均频谱分量和噪声平均频谱分量。

公开(公告)号：US10802393B2

公开(公告)日：2020-10-13

申请号：US15784408

申请日：2017-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Obert R. Wood, II ,  Genevieve Beique ,  Yulu Chen ,  Erik Verduijn ,  Francis Goodwin

IPC: G03F1/24 ,  G03F1/58 ,  G03F1/80

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an extreme ultraviolet (EUV) lithography mask and methods of manufacture. The EUV mask structure includes: a reflective layer; a capping material on the reflective layer; a buffer layer on the capping layer; alternating absorber layers on the buffer layer; and a capping layer on the top of the alternating absorber layers.

公开(公告)号：US20200312764A1

公开(公告)日：2020-10-01

申请号：US16363585

申请日：2019-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Ruilong Xie ,  Lei Sun

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.

公开(公告)号：US10782606B2

公开(公告)日：2020-09-22

申请号：US16022752

申请日：2018-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yong Liang ,  Lei Sun ,  Yongan Xu ,  Craig D. Higgins

IPC: G03F1/22 ,  G03F7/20

Abstract: Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is “self-biased”). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer. Movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer improves photoresist layer development and pattern resolution.

公开(公告)号：US20190318927A1

公开(公告)日：2019-10-17

申请号：US15954066

申请日：2018-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Xunyuan Zhang ,  Frank W. Mont ,  Shao Beng Law

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02

Abstract: The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

公开(公告)号：US10388652B2

公开(公告)日：2019-08-20

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US10153162B2

公开(公告)日：2018-12-11

申请号：US15284773

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-Han Kim ,  Wenhui Wang ,  Azat Latypov ,  Tamer Coskun, Jr. ,  Lei Sun

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/66

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

公开(公告)号：US20180144979A1

公开(公告)日：2018-05-24

申请号：US15359037

申请日：2016-11-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao Beng Law ,  Genevieve Beique ,  Frank W. Mont ,  Lei Sun ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/76877 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/76802

Abstract: Methods of lithographic patterning. A metal hardmask layer is formed on a dielectric layer and a patterned layer is formed on the metal hardmask layer. A metal layer is formed on an area of the metal hardmask layer exposed by an opening in the patterned layer. After the metal layer is formed, the patterned layer is removed from the metal hardmask layer. After the patterned layer is removed, the metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

公开(公告)号：US09595478B2

公开(公告)日：2017-03-14

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。