公开(公告)号：US20200175293A1

公开(公告)日：2020-06-04

申请号：US16694899

申请日：2019-11-25

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho HAN ,  Young-Su KWON ,  Yong Cheol Peter CHO ,  Min-Seok CHOI

IPC: G06K9/03 ,  G06F1/06 ,  G06F11/14 ,  G06K9/00 ,  G06T1/60

Abstract: Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores arranged in rows and columns and configured to perform a pattern recognition operation on an input feature using a kernel coefficient in response to each instruction, an instruction memory configured to provide the instruction to each of the plurality of nano cores, a feature memory configured to provide the input feature to each of the plurality of nano cores, a kernel memory configured to provide the kernel coefficients to the plurality of nano cores, and a functional safety processor core configured to receive a result of a pattern recognition operation outputted from the plurality of nano cores to detect the presence of a recognition error, and perform a fault tolerance function on the detected recognition error.

公开(公告)号：US20190114236A1

公开(公告)日：2019-04-18

申请号：US16022334

申请日：2018-06-28

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho HAN ,  Min-Seok CHOI ,  Young-Su KWON

IPC: G06F11/16 ,  G06F11/20 ,  G06F15/78

Abstract: A network on-chip may include a master circuit that outputs write data or receives read data, a slave circuit that stores the write data or outputs the read data, a master network interface circuit that generates a first error correction code associated with the write data, a slave network interface circuit that generates a second error correction code associated with the read data, and an on-chip network circuit that transmits the write data and the first error correction code to the slave network interface circuit or transmits the read data and the second error correction code to the master network interface circuit, the master network interface circuit decodes the read data and the second error correction code and requests the read data again or generates a first fault signal, and the slave network interface circuit decodes the write data and the first error correction code and requests the write data again or generates a second fault signal.

公开(公告)号：US20150143049A1

公开(公告)日：2015-05-21

申请号：US14253349

申请日：2014-04-15

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho HAN ,  Young Su KWON ,  Kyoung Seon SHIN

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F12/0833

Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

Abstract translation: 提供了一种缓存控制装置和方法，当多个处理器从芯片中的相同存储器读取程序时，保持数据的一致性和由高速缓存存储器生成的指令。 高速缓存控制装置包括：一致性控制器客户端，被配置为包括MESI寄存器，该MESI寄存器包括在指令高速缓存中，并且存储针对每行的修改状态，独占状态，共享状态和无效状态中的至少一个 指令高速缓存以及连接到一致性控制器并被配置为发送和接收广播地址信息，读取或写入信息以及将指向或从指令高速缓冲存储器中的另一个高速缓存的信息命中或丢失的一致性接口。

公开(公告)号：US20150006935A1

公开(公告)日：2015-01-01

申请号：US14300942

申请日：2014-06-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jin Ho HAN ,  Young Su KWON ,  Kyoung Seon SHIN ,  Kyung Jin BYUN ,  Nak Woong EUM

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

Abstract: Disclosed are a processor capable of reducing power consumption of a cache by controlling power mode of the cache and a method for the same. A processor may comprise a processor core; a cache storing instructions to be executed in the processor core; and a cache management part controlling the cache based on a processor operation mode indicating a state of the processor core determined according to algorithm executed in the processor core. Thus, power consumption of cache may be reduced, and degradation of processor core performance may be prevented by controlling power mode of cache considering an operation mode of the processor.

Abstract translation: 公开了一种能够通过控制高速缓存的功率模式来降低高速缓存的功耗的处理器及其方法。 处理器可以包括处理器核心; 存储要在处理器核心中执行的指令的高速缓存; 以及高速缓存管理部，其基于指示根据在所述处理器核心中执行的算法确定的所述处理器核心的状态的处理器操作模式来控制所述高速缓存。 因此，可以降低高速缓存的功率消耗，并且可以通过考虑处理器的操作模式来控制高速缓存的功率模式来防止处理器核心性能的劣化。